LXR uboot/board/freescale/ls2080ardb/eth

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2015 Freescale Semiconductor, Inc.
   4 *
   5 */
   6
   7#include <common.h>
   8#include <command.h>
   9#include <net.h>
  10#include <netdev.h>
  11#include <malloc.h>
  12#include <fsl_mdio.h>
  13#include <miiphy.h>
  14#include <phy.h>
  15#include <fm_eth.h>
  16#include <asm/global_data.h>
  17#include <asm/io.h>
  18#include <exports.h>
  19#include <asm/arch/fsl_serdes.h>
  20#include <fsl-mc/fsl_mc.h>
  21#include <fsl-mc/ldpaa_wriop.h>
  22
  23DECLARE_GLOBAL_DATA_PTR;
  24
  25int board_eth_init(struct bd_info *bis)
  26{
  27#ifndef CONFIG_DM_ETH
  28#if defined(CONFIG_FSL_MC_ENET)
  29        int i, interface;
  30        struct memac_mdio_info mdio_info;
  31        struct mii_dev *dev;
  32        struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  33        u32 srds_s1;
  34        struct memac_mdio_controller *reg;
  35
  36        srds_s1 = in_le32(&gur->rcwsr[28]) &
  37                                FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  38        srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  39
  40        reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  41        mdio_info.regs = reg;
  42        mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  43
  44        /* Register the EMI 1 */
  45        fm_memac_mdio_init(bis, &mdio_info);
  46
  47        reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  48        mdio_info.regs = reg;
  49        mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  50
  51        /* Register the EMI 2 */
  52        fm_memac_mdio_init(bis, &mdio_info);
  53
  54        switch (srds_s1) {
  55        case 0x2A:
  56                wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
  57                wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
  58                wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
  59                wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
  60                wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
  61                wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
  62                wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
  63                wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
  64
  65                break;
  66        case 0x4B:
  67                wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
  68                wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
  69                wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
  70                wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
  71
  72                break;
  73        default:
  74                printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
  75                       srds_s1);
  76                break;
  77        }
  78
  79        for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
  80                interface = wriop_get_enet_if(i);
  81                switch (interface) {
  82                case PHY_INTERFACE_MODE_XGMII:
  83                        dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  84                        wriop_set_mdio(i, dev);
  85                        break;
  86                default:
  87                        break;
  88                }
  89        }
  90
  91        for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
  92                switch (wriop_get_enet_if(i)) {
  93                case PHY_INTERFACE_MODE_XGMII:
  94                        dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  95                        wriop_set_mdio(i, dev);
  96                        break;
  97                default:
  98                        break;
  99                }
 100        }
 101
 102        cpu_eth_init(bis);
 103#endif /* CONFIG_FSL_MC_ENET */
 104#endif /* !CONFIG_DM_ETH */
 105
 106#ifdef CONFIG_PHY_AQUANTIA
 107        /*
 108         * Export functions to be used by AQ firmware
 109         * upload application
 110         */
 111        gd->jt->strcpy = strcpy;
 112        gd->jt->mdelay = mdelay;
 113        gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 114        gd->jt->phy_find_by_mask = phy_find_by_mask;
 115        gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 116        gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 117#endif
 118
 119#ifdef CONFIG_DM_ETH
 120        return 0;
 121#else
 122        return pci_eth_init(bis);
 123#endif
 124}
 125
 126#if defined(CONFIG_RESET_PHY_R)
 127void reset_phy(void)
 128{
 129        mc_env_boot();
 130}
 131#endif /* CONFIG_RESET_PHY_R */
 132