1# SPDX-License-Identifier: GPL-2.0+ 2# 3# (C) Copyright 2010 4# Heiko Schocher, DENX Software Engineering, hs@denx.de. 5# 6# (C) Copyright 2012 7# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 8# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com 9# 10# (C) Copyright 2012 11# 12# Refer doc/README.kwbimage for more details about how-to configure 13# and create kirkwood boot image 14# 15 16# Boot Media configurations 17BOOT_FROM spi # Boot from SPI flash 18 19DATA 0xFFD10000 0x01112222 # MPP Control 0 Register 20# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 21# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) 22# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) 23# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) 24# bit 19-16: 1, MPPSel4 NF_IO[6] 25# bit 23-20: 1, MPPSel5 NF_IO[7] 26# bit 27-24: 1, MPPSel6 SYSRST_O 27# bit 31-28: 0, MPPSel7 GPO[7] 28 29DATA 0xFFD10004 0x03303300 # MPP Control 1 Register 30# bit 3-0: 0, MPPSel8 GPIO[8] 31# bit 7-4: 0, MPPSel9 GPIO[9] 32# bit 12-8: 3, MPPSel10 UA0_TXD 33# bit 15-12: 3, MPPSel11 UA0_RXD 34# bit 19-16: 0, MPPSel12 not connected 35# bit 23-20: 3, MPPSel13 UA1_TXD 36# bit 27-24: 3, MPPSel14 UA1_RXD 37# bit 31-28: 0, MPPSel15 GPIO[15] 38 39DATA 0xFFD10008 0x00001100 # MPP Control 2 Register 40# bit 3-0: 0, MPPSel16 GPIO[16] 41# bit 7-4: 0, MPPSel17 not connected 42# bit 12-8: 1, MPPSel18 NF_IO[0] 43# bit 15-12: 1, MPPSel19 NF_IO[1] 44# bit 19-16: 0, MPPSel20 GPIO[20] 45# bit 23-20: 0, MPPSel21 GPIO[21] 46# bit 27-24: 0, MPPSel22 GPIO[22] 47# bit 31-28: 0, MPPSel23 GPIO[23] 48 49# MPP Control 3-6 Register untouched (MPP24-49) 50 51DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register 52# bit 2-0: 3, Reserved 53# bit 5-3: 3, Reserved 54# bit 6: 0, Reserved 55# bit 7: 0, RGMII-pads voltage = 3.3V 56# bit 10-8: 3, Reserved 57# bit 13-11: 3, Reserved 58# bit 14: 0, Reserved 59# bit 15: 0, MPP RGMII-pads voltage = 3.3V 60# bit 31-16 0x1B1B, Reserved 61 62DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register 63# bit 0-1: 2, Tag RAM RTC RAM0 64# bit 3-2: 1, Tag RAM WTC RAM0 65# bit 7-4: 6, Reserve 66# bit 9-8: 2, Valid RAM RTC RAM 67# bit 11-10: 1, Valid RAM WTC RAM 68# bit 13-12: 2, Dirty RAM RTC RAM 69# bit 15-14: 1, Dirty RAM WTC RAM 70# bit 17-16: 2, Data RAM RTC RAM0 71# bit 19-18: 1, Data RAM WTC RAM0 72# bit 21-20: 2, Data RAM RTC RAM1 73# bit 23-22: 1, Data RAM WTC RAM1 74# bit 25-24: 2, Data RAM RTC RAM2 75# bit 27-26: 1, Data RAM WTC RAM2 76# bit 29-28: 2, Data RAM RTC RAM3 77# bit 31-30: 1, Data RAM WTC RAM4 78 79DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register 80# bit 15-0: ???, Reserve 81# bit 17-16: 2, ECC RAM RTC RAM0 82# bit 19-18: 1, ECC RAM WTC RAM0 83# bit 31-20: ???,Reserve 84 85# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! 86# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage 87 88# SDRAM initalization 89DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register 90# bit 13-0: 0x4E0, DDR2 clks refresh rate 91# bit 14: 0, reserved 92# bit 15: 0, reserved 93# bit 16: 0, CPU to Dram Write buffer policy 94# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic 95# bit 19-18: 0, reserved 96# bit 23-20: 0, reserved 97# bit 24: 1, enable exit self refresh mode on DDR access 98# bit 25: 1, required 99# bit 29-26: 0, reserved 100# bit 31-30: 1, reserved 101 102DATA 0xFFD01404 0x36543000 # DDR Controller Control Low 103# bit 3-0: 0, reserved 104# bit 4: 0, 2T mode =addr/cmd in same cycle 105# bit 5: 0, clk is driven during self refresh, we don't care for APX 106# bit 6: 0, use recommended falling edge of clk for addr/cmd 107# bit 7-11: 0, reserved 108# bit 12-13: 1, reserved, required 1 109# bit 14: 0, input buffer always powered up 110# bit 17-15: 0, reserved 111# bit 18: 1, cpu lock transaction enabled 112# bit 19: 0, reserved 113# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 114# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM 115# bit 30-28: 3, required 116# bit 31: 0,no additional STARTBURST delay 117 118DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) 119# bit 3-0: 0xE, TRAS, 15 clk (45 ns) 120# bit 7-4: 0x4, TRCD, 5 clk (15 ns) 121# bit 11-8: 0x4, TRP, 5 clk (15 ns) 122# bit 15-12: 0x4, TWR, 5 clk (15 ns) 123# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) 124# bit 20: 0, extended TRAS msb 125# bit 23-21: 0, reserved 126# bit 27-24: 0x3, TRRD, 4 clk (10 ns) 127# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) 128 129DATA 0xFFD0140C 0x0000003e # DDR Timing (High) 130# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) 131# bit 8-7: 0, TR2R 132# bit 10-9: 0, TR2W 133# bit 12-11: 0, TW2W 134# bit 31-13: 0, reserved 135 136DATA 0xFFD01410 0x00000001 # DDR Address Control 137# bit 1-0: 1, Cs0width=x16 138# bit 3-2: 0, Cs0size=2Gb 139# bit 5-4: 0, Cs1width=nonexistent 140# bit 7-6: 0, Cs1size =nonexistent 141# bit 9-8: 0, Cs2width=nonexistent 142# bit 11-10: 0, Cs2size =nonexistent 143# bit 13-12: 0, Cs3width=nonexistent 144# bit 15-14: 0, Cs3size =nonexistent 145# bit 16: 0, Cs0AddrSel 146# bit 17: 0, Cs1AddrSel 147# bit 18: 0, Cs2AddrSel 148# bit 19: 0, Cs3AddrSel 149# bit 31-20: 0, required 150 151DATA 0xFFD01414 0x00000000 # DDR Open Pages Control 152# bit 0: 0, OpenPage enabled 153# bit 31-1: 0, required 154 155DATA 0xFFD01418 0x00000000 # DDR Operation 156# bit 3-0: 0, DDR cmd 157# bit 31-4: 0, required 158 159DATA 0xFFD0141C 0x00000652 # DDR Mode 160# bit 2-0: 2, Burst Length = 4 161# bit 3: 0, Burst Type 162# bit 6-4: 5, CAS Latency = 5 163# bit 7: 0, Test mode 164# bit 8: 0, DLL Reset 165# bit 11-9: 3, Write recovery for auto-precharge must be 3 166# bit 12: 0, Active power down exit time, fast exit 167# bit 14-13: 0, reserved 168# bit 31-15: 0, reserved 169 170DATA 0xFFD01420 0x00000006 # DDR Extended Mode 171# bit 0: 0, DDR DLL enabled 172# bit 1: 1, DDR drive strength reduced 173# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] 174# bit 5-3: 0, required 175# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] 176# bit 9-7: 0, required 177# bit 10: 0, differential DQS enabled 178# bit 11: 0, required 179# bit 12: 0, DDR output buffer enabled 180# bit 31-13: 0 required 181 182DATA 0xFFD01424 0x0000F17F # DDR Controller Control High 183# bit 2-0: 7, required 184# bit 3: 1, MBUS Burst Chop disabled 185# bit 6-4: 7, required 186# bit 7: 0, reserved 187# bit 8: 1, add sample stage required for f > 266 MHz 188# bit 9: 0, no half clock cycle addition to dataout 189# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 190# bit 11: 0, 1/4 clock cycle skew disabled for write mesh 191# bit 15-12:0xf, required 192# bit 31-16: 0, required 193 194DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low 195# bit 3-0: 0, required 196# bit 7-4: 2, M_ODT assertion 2 cycles after read start command 197# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command 198# (ODT turn off delay 2,5 clk cycles) 199# bit 15-12: 4, internal ODT time based on bit 7-4 200# with the considered SDRAM internal delay 201# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 202# with the considered SDRAM internal delay 203# bit 31-20: 0, required 204 205DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High 206# bit 3-0: 2, M_ODT assertion same as bit 11-8 207# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 208# bit 11-8: 4, internal ODT assertion 2 cycles after write start command 209# with the considered SDRAM internal delay 210# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command 211# with the considered SDRAM internal delay 212 213DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 214# bit 23-0: 0, reserved 215# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] 216 217DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 218# bit 0: 1, Window enabled 219# bit 1: 0, Write Protect disabled 220# bit 3-2: 0, CS0 hit selected 221# bit 23-4:ones, required 222# bit 31-24: 0x0F, Size (i.e. 256MB) 223 224DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 225DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 226DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 227 228DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) 229# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 230# bit 7-4: 0, ODT0Rd, MODT[1] not asserted 231# bit 11-8: 0, required 232# big 15-11: 0, required 233# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 234# bit 23-20: 0, ODT0Wr, MODT[1] not asserted 235# bit 27-24: 0, required 236# bit 31-28: 0, required 237 238DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 239# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above 240# bit 3-2: 0, ODT1 controlled by register 241# bit 31-4: 0, required 242 243DATA 0xFFD0149C 0x0000E801 # CPU ODT Control 244# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 245# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM 246# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr 247# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm 248# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm 249# bit 14: 1, STARTBURST ODT enabled 250# bit 15: 1, Use ODT Block 251 252DATA 0xFFD01480 0x00000001 # DDR Initialization Control 253# bit 0: 1, enable DDR init upon this register write 254# bit 31-1: 0, reserved 255 256# End of Header extension 257DATA 0x0 0x0 258