LXR uboot/board/phytec/phycore

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
   4 * Author: Teresa Remmet <t.remmet@phytec.de>
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/clock.h>
   9#include <asm/arch/ddr.h>
  10#include <asm/arch/imx8mm_pins.h>
  11#include <asm/arch/sys_proto.h>
  12#include <asm/global_data.h>
  13#include <asm/mach-imx/boot_mode.h>
  14#include <asm/mach-imx/iomux-v3.h>
  15#include <hang.h>
  16#include <init.h>
  17#include <log.h>
  18#include <spl.h>
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22int spl_board_boot_device(enum boot_device boot_dev_spl)
  23{
  24        switch (boot_dev_spl) {
  25        case SD2_BOOT:
  26        case MMC2_BOOT:
  27                return BOOT_DEVICE_MMC1;
  28        case SD3_BOOT:
  29        case MMC3_BOOT:
  30                return BOOT_DEVICE_MMC2;
  31        case QSPI_BOOT:
  32                return BOOT_DEVICE_NOR;
  33        case USB_BOOT:
  34                return BOOT_DEVICE_BOARD;
  35        default:
  36                return BOOT_DEVICE_NONE;
  37        }
  38}
  39
  40static void spl_dram_init(void)
  41{
  42        ddr_init(&dram_timing);
  43}
  44
  45void spl_board_init(void)
  46{
  47        /* Serial download mode */
  48        if (is_usb_boot()) {
  49                puts("Back to ROM, SDP\n");
  50                restore_boot_params();
  51        }
  52        puts("Normal Boot\n");
  53}
  54
  55int board_fit_config_name_match(const char *name)
  56{
  57        return 0;
  58}
  59
  60#define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  61#define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE)
  62
  63static iomux_v3_cfg_t const uart_pads[] = {
  64        IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  65        IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  66};
  67
  68static iomux_v3_cfg_t const wdog_pads[] = {
  69        IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  70};
  71
  72int board_early_init_f(void)
  73{
  74        struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  75
  76        imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  77
  78        set_wdog_reset(wdog);
  79
  80        imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  81
  82        return 0;
  83}
  84
  85void board_init_f(ulong dummy)
  86{
  87        int ret;
  88
  89        arch_cpu_init();
  90
  91        init_uart_clk(2);
  92
  93        board_early_init_f();
  94
  95        preloader_console_init();
  96
  97        /* Clear the BSS. */
  98        memset(__bss_start, 0, __bss_end - __bss_start);
  99
 100        ret = spl_early_init();
 101        if (ret) {
 102                debug("spl_early_init() failed: %d\n", ret);
 103                hang();
 104        }
 105
 106        enable_tzc380();
 107
 108        /* DDR initialization */
 109        spl_dram_init();
 110
 111        board_init_r(NULL, 0);
 112}
 113