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9#include <common.h>
10#include <cpu_func.h>
11#include <dm.h>
12#include <image.h>
13#include <init.h>
14#include <net.h>
15#include <asm/global_data.h>
16#include <linux/bitops.h>
17#include <linux/delay.h>
18
19#include <ahci.h>
20#include <asm/arch/clock.h>
21#include <asm/arch/crm_regs.h>
22#include <asm/arch/imx-regs.h>
23#include <asm/arch/mx6-ddr.h>
24#include <asm/arch/mx6-pins.h>
25#include <asm/arch/mxc_hdmi.h>
26#include <asm/arch/sys_proto.h>
27#include <asm/bootm.h>
28#include <asm/gpio.h>
29#include <asm/mach-imx/boot_mode.h>
30#include <asm/mach-imx/iomux-v3.h>
31#include <asm/mach-imx/sata.h>
32#include <asm/mach-imx/video.h>
33#include <dm/device-internal.h>
34#include <dm/platform_data/serial_mxc.h>
35#include <dwc_ahsata.h>
36#include <env.h>
37#include <fsl_esdhc_imx.h>
38#include <imx_thermal.h>
39#include <micrel.h>
40#include <miiphy.h>
41#include <netdev.h>
42
43#include "../common/tdx-cfg-block.h"
44#ifdef CONFIG_TDX_CMD_IMX_MFGR
45#include "pf0100.h"
46#endif
47
48DECLARE_GLOBAL_DATA_PTR;
49
50#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
54#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
55 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
56 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
57
58#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
59 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
60 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
61
62#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
64
65#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
67 PAD_CTL_SRE_SLOW)
68
69#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
70 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
71 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
72
73#define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
74
75#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
76
77#define APALIS_IMX6_SATA_INIT_RETRIES 10
78
79int dram_init(void)
80{
81
82 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
83 (ulong)imx_ddr_size());
84
85 return 0;
86}
87
88
89iomux_v3_cfg_t const uart1_pads_dce[] = {
90 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
91 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
92};
93iomux_v3_cfg_t const uart1_pads_dte[] = {
94 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
95 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
96};
97
98#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
99
100iomux_v3_cfg_t const usdhc1_pads[] = {
101 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
112# define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
113};
114
115
116iomux_v3_cfg_t const usdhc2_pads[] = {
117 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
124# define GPIO_SD_CD IMX_GPIO_NR(6, 14)
125};
126
127
128iomux_v3_cfg_t const usdhc3_pads[] = {
129 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
130 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
131 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
132 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
133 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
134 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
135 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
136 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
137 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
138 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
139 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
140};
141#endif
142
143int mx6_rgmii_rework(struct phy_device *phydev)
144{
145 int tmp;
146
147 switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
148 case PHY_ID_KSZ9131:
149
150 tmp = ksz9031_phy_extended_read(phydev, 0x02,
151 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
152 MII_KSZ9031_MOD_DATA_NO_POST_INC);
153
154 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
155
156 ksz9031_phy_extended_write(phydev, 0x02,
157 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
158 MII_KSZ9031_MOD_DATA_NO_POST_INC,
159 tmp);
160
161 tmp = ksz9031_phy_extended_read(phydev, 0x02,
162 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
163 MII_KSZ9031_MOD_DATA_NO_POST_INC);
164
165 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
166
167 ksz9031_phy_extended_write(phydev, 0x02,
168 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
169 MII_KSZ9031_MOD_DATA_NO_POST_INC,
170 tmp);
171
172
173 ksz9031_phy_extended_write(phydev, 0x02,
174 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
175 MII_KSZ9031_MOD_DATA_NO_POST_INC,
176 0x007d);
177
178 ksz9031_phy_extended_write(phydev, 0x02,
179 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
180 MII_KSZ9031_MOD_DATA_NO_POST_INC,
181 0x7777);
182
183 ksz9031_phy_extended_write(phydev, 0x02,
184 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
185 MII_KSZ9031_MOD_DATA_NO_POST_INC,
186 0xdddd);
187
188 ksz9031_phy_extended_write(phydev, 0x02,
189 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
190 MII_KSZ9031_MOD_DATA_NO_POST_INC,
191 0x0007);
192 break;
193 case PHY_ID_KSZ9031:
194 default:
195
196 ksz9031_phy_extended_write(phydev, 0x02,
197 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
198 MII_KSZ9031_MOD_DATA_NO_POST_INC,
199 0x0000);
200
201 ksz9031_phy_extended_write(phydev, 0x02,
202 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
203 MII_KSZ9031_MOD_DATA_NO_POST_INC,
204 0x0000);
205
206 ksz9031_phy_extended_write(phydev, 0x02,
207 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
208 MII_KSZ9031_MOD_DATA_NO_POST_INC,
209 0x0000);
210
211 ksz9031_phy_extended_write(phydev, 0x02,
212 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
213 MII_KSZ9031_MOD_DATA_NO_POST_INC,
214 0x03FF);
215 break;
216 }
217
218 return 0;
219}
220
221iomux_v3_cfg_t const enet_pads[] = {
222 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
223 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
224 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
225 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
237
238 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
239 MUX_MODE_SION,
240# define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
241};
242
243
244iomux_v3_cfg_t const gpio_pads[] = {
245
246 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
247 MUX_MODE_SION,
248 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
249 MUX_MODE_SION,
250 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
251 MUX_MODE_SION,
252 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
253 MUX_MODE_SION,
254 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
255 MUX_MODE_SION,
256 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
257 MUX_MODE_SION,
258 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
259 MUX_MODE_SION,
260 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
261 MUX_MODE_SION,
262 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
263 MUX_MODE_SION,
264};
265
266static void setup_iomux_gpio(void)
267{
268 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
269}
270
271iomux_v3_cfg_t const usb_pads[] = {
272
273 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
274# define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
275
276 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
277# define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
278
279 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
280
281 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
282# define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
283};
284
285
286
287
288
289#define UCR3 0x88
290#define UCR3_RI BIT(8)
291#define UCR3_DCD BIT(9)
292#define UFCR 0x90
293#define UFCR_DCEDTE BIT(6)
294
295static void setup_dtemode_uart(void)
296{
297 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
298 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
299 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
300 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
301
302 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
303 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
304 clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
305 clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
306}
307static void setup_dcemode_uart(void)
308{
309 clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
310 clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
311 clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
312 clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
313}
314
315static void setup_iomux_dte_uart(void)
316{
317 setup_dtemode_uart();
318 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
319 ARRAY_SIZE(uart1_pads_dte));
320}
321static void setup_iomux_dce_uart(void)
322{
323 setup_dcemode_uart();
324 imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
325 ARRAY_SIZE(uart1_pads_dce));
326}
327
328#ifdef CONFIG_USB_EHCI_MX6
329int board_ehci_hcd_init(int port)
330{
331 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
332 return 0;
333}
334#endif
335
336#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
337
338struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
339 {USDHC3_BASE_ADDR},
340 {USDHC1_BASE_ADDR},
341 {USDHC2_BASE_ADDR},
342};
343
344int board_mmc_getcd(struct mmc *mmc)
345{
346 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
347 int ret = true;
348
349 switch (cfg->esdhc_base) {
350 case USDHC1_BASE_ADDR:
351 gpio_request(GPIO_MMC_CD, "MMC_CD");
352 gpio_direction_input(GPIO_MMC_CD);
353 ret = !gpio_get_value(GPIO_MMC_CD);
354 break;
355 case USDHC2_BASE_ADDR:
356 gpio_request(GPIO_MMC_CD, "SD_CD");
357 gpio_direction_input(GPIO_SD_CD);
358 ret = !gpio_get_value(GPIO_SD_CD);
359 break;
360 }
361
362 return ret;
363}
364
365int board_mmc_init(struct bd_info *bis)
366{
367 struct src *psrc = (struct src *)SRC_BASE_ADDR;
368 unsigned reg = readl(&psrc->sbmr1) >> 11;
369
370
371
372
373
374
375
376
377
378 switch (reg & 0x3) {
379 case 0x0:
380 imx_iomux_v3_setup_multiple_pads(
381 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
382 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
383 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
384 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
385 break;
386 case 0x1:
387 imx_iomux_v3_setup_multiple_pads(
388 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
389 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
390 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
391 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
392 break;
393 case 0x2:
394 imx_iomux_v3_setup_multiple_pads(
395 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
396 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
397 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
398 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
399 break;
400 default:
401 puts("MMC boot device not available");
402 }
403
404 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
405}
406#endif
407
408int board_phy_config(struct phy_device *phydev)
409{
410 mx6_rgmii_rework(phydev);
411 if (phydev->drv->config)
412 phydev->drv->config(phydev);
413
414 return 0;
415}
416
417static iomux_v3_cfg_t const pwr_intb_pads[] = {
418
419
420
421
422 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
423};
424
425#if defined(CONFIG_VIDEO_IPUV3)
426
427static iomux_v3_cfg_t const backlight_pads[] = {
428
429 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
430 MUX_MODE_SION,
431#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
432
433 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
434
435 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
436 MUX_MODE_SION,
437#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
438
439 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
440#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
441
442 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
443 MUX_MODE_SION,
444#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
445};
446
447static iomux_v3_cfg_t const rgb_pads[] = {
448 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
449 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
450 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
451 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
452 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
453 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
454 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
455 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
456 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
457 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
458 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
459 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
460 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
461 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
462 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
463 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
464 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
465 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
466 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
467 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
468 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
469 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
470 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
471 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
472 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
473 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
474 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
475 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
476};
477
478static void do_enable_hdmi(struct display_info_t const *dev)
479{
480 imx_enable_hdmi_phy();
481}
482
483static void enable_lvds(struct display_info_t const *dev)
484{
485 struct iomuxc *iomux = (struct iomuxc *)
486 IOMUXC_BASE_ADDR;
487 u32 reg = readl(&iomux->gpr[2]);
488 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
489 writel(reg, &iomux->gpr[2]);
490 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
491 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
492 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
493}
494
495static void enable_rgb(struct display_info_t const *dev)
496{
497 imx_iomux_v3_setup_multiple_pads(
498 rgb_pads,
499 ARRAY_SIZE(rgb_pads));
500 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
501 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
502 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
503}
504
505static int detect_default(struct display_info_t const *dev)
506{
507 (void) dev;
508 return 1;
509}
510
511struct display_info_t const displays[] = {{
512 .bus = -1,
513 .addr = 0,
514 .pixfmt = IPU_PIX_FMT_RGB24,
515 .detect = detect_hdmi,
516 .enable = do_enable_hdmi,
517 .mode = {
518 .name = "HDMI",
519 .refresh = 60,
520 .xres = 1024,
521 .yres = 768,
522 .pixclock = 15385,
523 .left_margin = 220,
524 .right_margin = 40,
525 .upper_margin = 21,
526 .lower_margin = 7,
527 .hsync_len = 60,
528 .vsync_len = 10,
529 .sync = FB_SYNC_EXT,
530 .vmode = FB_VMODE_NONINTERLACED
531} }, {
532 .bus = -1,
533 .addr = 0,
534 .di = 1,
535 .pixfmt = IPU_PIX_FMT_RGB24,
536 .detect = detect_default,
537 .enable = enable_rgb,
538 .mode = {
539 .name = "vga-rgb",
540 .refresh = 60,
541 .xres = 640,
542 .yres = 480,
543 .pixclock = 33000,
544 .left_margin = 48,
545 .right_margin = 16,
546 .upper_margin = 31,
547 .lower_margin = 11,
548 .hsync_len = 96,
549 .vsync_len = 2,
550 .sync = 0,
551 .vmode = FB_VMODE_NONINTERLACED
552} }, {
553 .bus = -1,
554 .addr = 0,
555 .di = 1,
556 .pixfmt = IPU_PIX_FMT_RGB24,
557 .enable = enable_rgb,
558 .mode = {
559 .name = "wvga-rgb",
560 .refresh = 60,
561 .xres = 800,
562 .yres = 480,
563 .pixclock = 25000,
564 .left_margin = 40,
565 .right_margin = 88,
566 .upper_margin = 33,
567 .lower_margin = 10,
568 .hsync_len = 128,
569 .vsync_len = 2,
570 .sync = 0,
571 .vmode = FB_VMODE_NONINTERLACED
572} }, {
573 .bus = -1,
574 .addr = 0,
575 .pixfmt = IPU_PIX_FMT_LVDS666,
576 .enable = enable_lvds,
577 .mode = {
578 .name = "wsvga-lvds",
579 .refresh = 60,
580 .xres = 1024,
581 .yres = 600,
582 .pixclock = 15385,
583 .left_margin = 220,
584 .right_margin = 40,
585 .upper_margin = 21,
586 .lower_margin = 7,
587 .hsync_len = 60,
588 .vsync_len = 10,
589 .sync = FB_SYNC_EXT,
590 .vmode = FB_VMODE_NONINTERLACED
591} } };
592size_t display_count = ARRAY_SIZE(displays);
593
594static void setup_display(void)
595{
596 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
597 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
598 int reg;
599
600 enable_ipu_clock();
601 imx_setup_hdmi();
602
603 reg = __raw_readl(&mxc_ccm->CCGR3);
604 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
605 writel(reg, &mxc_ccm->CCGR3);
606
607
608 reg = readl(&mxc_ccm->cs2cdr);
609 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
610 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
611 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
612 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
613 writel(reg, &mxc_ccm->cs2cdr);
614
615 reg = readl(&mxc_ccm->cscmr2);
616 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
617 writel(reg, &mxc_ccm->cscmr2);
618
619 reg = readl(&mxc_ccm->chsccdr);
620 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
621 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
622 writel(reg, &mxc_ccm->chsccdr);
623
624 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
625 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
626 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
627 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
628 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
629 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
630 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
631 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
632 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
633 writel(reg, &iomux->gpr[2]);
634
635 reg = readl(&iomux->gpr[3]);
636 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
637 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
638 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
639 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
640 writel(reg, &iomux->gpr[3]);
641
642
643 imx_iomux_v3_setup_multiple_pads(backlight_pads,
644 ARRAY_SIZE(backlight_pads));
645
646 gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
647 gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
648 gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
649 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
650 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
651 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
652}
653
654
655
656
657void board_preboot_os(void)
658{
659 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
660 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
661}
662#endif
663
664int board_early_init_f(void)
665{
666 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
667 ARRAY_SIZE(pwr_intb_pads));
668#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
669 setup_iomux_dte_uart();
670#else
671 setup_iomux_dce_uart();
672#endif
673 return 0;
674}
675
676
677
678
679
680int overwrite_console(void)
681{
682 return 1;
683}
684
685int board_init(void)
686{
687
688 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
689
690#if defined(CONFIG_VIDEO_IPUV3)
691 setup_display();
692#endif
693
694#ifdef CONFIG_TDX_CMD_IMX_MFGR
695 (void) pmic_init();
696#endif
697
698#ifdef CONFIG_SATA
699 setup_sata();
700#endif
701
702 setup_iomux_gpio();
703
704 return 0;
705}
706
707#ifdef CONFIG_BOARD_LATE_INIT
708int board_late_init(void)
709{
710#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
711 char env_str[256];
712 u32 rev;
713
714 rev = get_board_revision();
715 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
716 env_set("board_rev", env_str);
717
718#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
719 if ((rev & 0xfff0) == 0x0100) {
720 char *fdt_env;
721
722
723 setup_iomux_dce_uart();
724
725
726 fdt_env = env_get("fdt_file");
727 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
728 env_set("fdt_file", FDT_FILE_V1_0);
729 printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
730#ifndef CONFIG_ENV_IS_NOWHERE
731 env_save();
732#endif
733 }
734 }
735#endif
736#endif
737
738#ifdef CONFIG_CMD_USB_SDP
739 if (is_boot_from_usb()) {
740 printf("Serial Downloader recovery mode, using sdp command\n");
741 env_set("bootdelay", "0");
742 env_set("bootcmd", "sdp 0");
743 }
744#endif
745
746 return 0;
747}
748#endif
749
750int checkboard(void)
751{
752 char it[] = " IT";
753 int minc, maxc;
754
755 switch (get_cpu_temp_grade(&minc, &maxc)) {
756 case TEMP_AUTOMOTIVE:
757 case TEMP_INDUSTRIAL:
758 break;
759 case TEMP_EXTCOMMERCIAL:
760 default:
761 it[0] = 0;
762 };
763 printf("Model: Toradex Apalis iMX6 %s %s%s\n",
764 is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
765 (gd->ram_size == 0x80000000) ? "2GB" :
766 (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
767 return 0;
768}
769
770#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
771int ft_board_setup(void *blob, struct bd_info *bd)
772{
773 return ft_common_board_setup(blob, bd);
774}
775#endif
776
777#ifdef CONFIG_CMD_BMODE
778static const struct boot_mode board_boot_modes[] = {
779
780 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
781 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
782 {NULL, 0},
783};
784#endif
785
786int misc_init_r(void)
787{
788#ifdef CONFIG_CMD_BMODE
789 add_board_boot_modes(board_boot_modes);
790#endif
791 return 0;
792}
793
794#ifdef CONFIG_LDO_BYPASS_CHECK
795
796void ldo_mode_set(int ldo_bypass)
797{
798 return;
799}
800#endif
801
802#ifdef CONFIG_SPL_BUILD
803#include <spl.h>
804#include <linux/libfdt.h>
805#include "asm/arch/mx6q-ddr.h"
806#include "asm/arch/iomux.h"
807#include "asm/arch/crm_regs.h"
808
809static int mx6_com_dcd_table[] = {
810
811MX6_IOM_DRAM_SDQS0, 0x00000030,
812MX6_IOM_DRAM_SDQS1, 0x00000030,
813MX6_IOM_DRAM_SDQS2, 0x00000030,
814MX6_IOM_DRAM_SDQS3, 0x00000030,
815MX6_IOM_DRAM_SDQS4, 0x00000030,
816MX6_IOM_DRAM_SDQS5, 0x00000030,
817MX6_IOM_DRAM_SDQS6, 0x00000030,
818MX6_IOM_DRAM_SDQS7, 0x00000030,
819
820MX6_IOM_GRP_B0DS, 0x00000030,
821MX6_IOM_GRP_B1DS, 0x00000030,
822MX6_IOM_GRP_B2DS, 0x00000030,
823MX6_IOM_GRP_B3DS, 0x00000030,
824MX6_IOM_GRP_B4DS, 0x00000030,
825MX6_IOM_GRP_B5DS, 0x00000030,
826MX6_IOM_GRP_B6DS, 0x00000030,
827MX6_IOM_GRP_B7DS, 0x00000030,
828MX6_IOM_GRP_ADDDS, 0x00000030,
829
830MX6_IOM_GRP_CTLDS, 0x00000030,
831
832MX6_IOM_DRAM_DQM0, 0x00020030,
833MX6_IOM_DRAM_DQM1, 0x00020030,
834MX6_IOM_DRAM_DQM2, 0x00020030,
835MX6_IOM_DRAM_DQM3, 0x00020030,
836MX6_IOM_DRAM_DQM4, 0x00020030,
837MX6_IOM_DRAM_DQM5, 0x00020030,
838MX6_IOM_DRAM_DQM6, 0x00020030,
839MX6_IOM_DRAM_DQM7, 0x00020030,
840
841MX6_IOM_DRAM_CAS, 0x00020030,
842MX6_IOM_DRAM_RAS, 0x00020030,
843MX6_IOM_DRAM_SDCLK_0, 0x00020030,
844MX6_IOM_DRAM_SDCLK_1, 0x00020030,
845
846MX6_IOM_DRAM_RESET, 0x00020030,
847MX6_IOM_DRAM_SDCKE0, 0x00003000,
848MX6_IOM_DRAM_SDCKE1, 0x00003000,
849
850MX6_IOM_DRAM_SDODT0, 0x00003030,
851MX6_IOM_DRAM_SDODT1, 0x00003030,
852
853
854MX6_IOM_DDRMODE_CTL, 0x00020000,
855
856MX6_IOM_GRP_DDRMODE, 0x00020000,
857
858MX6_IOM_GRP_DDRPKE, 0x00000000,
859MX6_IOM_DRAM_SDBA2, 0x00000000,
860
861MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
862
863
864MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
865MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
866MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
867MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
868MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
869MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
870MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
871MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
872
873
874
875
876MX6_MMDC_P0_MDMISC, 0x00081740,
877
878
879
880
881MX6_MMDC_P0_MDSCR, 0x00008000,
882
883
884
885MX6_MMDC_P0_MDPDC, 0x00020036,
886MX6_MMDC_P0_MDCFG0, 0x555A7954,
887MX6_MMDC_P0_MDCFG1, 0xDB328F64,
888MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
889MX6_MMDC_P0_MDRWD, 0x000026D2,
890MX6_MMDC_P0_MDOR, 0x005A1023,
891MX6_MMDC_P0_MDOTC, 0x09555050,
892MX6_MMDC_P0_MDPDC, 0x00025576,
893MX6_MMDC_P0_MDASP, 0x00000027,
894MX6_MMDC_P0_MDCTL, 0x831A0000,
895MX6_MMDC_P0_MDSCR, 0x04088032,
896MX6_MMDC_P0_MDSCR, 0x00008033,
897MX6_MMDC_P0_MDSCR, 0x00428031,
898MX6_MMDC_P0_MDSCR, 0x19308030,
899MX6_MMDC_P0_MDSCR, 0x04008040,
900MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
901MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
902MX6_MMDC_P0_MDREF, 0x00005800,
903MX6_MMDC_P0_MPODTCTRL, 0x00000000,
904MX6_MMDC_P1_MPODTCTRL, 0x00000000,
905
906MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
907MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
908MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
909MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
910
911MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
912MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
913
914MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
915MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
916
917MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
918MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
919MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
920MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
921
922MX6_MMDC_P0_MPMUR0, 0x00000800,
923MX6_MMDC_P1_MPMUR0, 0x00000800,
924MX6_MMDC_P0_MDSCR, 0x00000000,
925MX6_MMDC_P0_MAPSR, 0x00011006,
926};
927
928static int mx6_it_dcd_table[] = {
929
930MX6_IOM_DRAM_SDQS0, 0x00000030,
931MX6_IOM_DRAM_SDQS1, 0x00000030,
932MX6_IOM_DRAM_SDQS2, 0x00000030,
933MX6_IOM_DRAM_SDQS3, 0x00000030,
934MX6_IOM_DRAM_SDQS4, 0x00000030,
935MX6_IOM_DRAM_SDQS5, 0x00000030,
936MX6_IOM_DRAM_SDQS6, 0x00000030,
937MX6_IOM_DRAM_SDQS7, 0x00000030,
938
939MX6_IOM_GRP_B0DS, 0x00000030,
940MX6_IOM_GRP_B1DS, 0x00000030,
941MX6_IOM_GRP_B2DS, 0x00000030,
942MX6_IOM_GRP_B3DS, 0x00000030,
943MX6_IOM_GRP_B4DS, 0x00000030,
944MX6_IOM_GRP_B5DS, 0x00000030,
945MX6_IOM_GRP_B6DS, 0x00000030,
946MX6_IOM_GRP_B7DS, 0x00000030,
947MX6_IOM_GRP_ADDDS, 0x00000030,
948
949MX6_IOM_GRP_CTLDS, 0x00000030,
950
951MX6_IOM_DRAM_DQM0, 0x00020030,
952MX6_IOM_DRAM_DQM1, 0x00020030,
953MX6_IOM_DRAM_DQM2, 0x00020030,
954MX6_IOM_DRAM_DQM3, 0x00020030,
955MX6_IOM_DRAM_DQM4, 0x00020030,
956MX6_IOM_DRAM_DQM5, 0x00020030,
957MX6_IOM_DRAM_DQM6, 0x00020030,
958MX6_IOM_DRAM_DQM7, 0x00020030,
959
960MX6_IOM_DRAM_CAS, 0x00020030,
961MX6_IOM_DRAM_RAS, 0x00020030,
962MX6_IOM_DRAM_SDCLK_0, 0x00020030,
963MX6_IOM_DRAM_SDCLK_1, 0x00020030,
964
965MX6_IOM_DRAM_RESET, 0x00020030,
966MX6_IOM_DRAM_SDCKE0, 0x00003000,
967MX6_IOM_DRAM_SDCKE1, 0x00003000,
968
969MX6_IOM_DRAM_SDODT0, 0x00003030,
970MX6_IOM_DRAM_SDODT1, 0x00003030,
971
972
973MX6_IOM_DDRMODE_CTL, 0x00020000,
974
975MX6_IOM_GRP_DDRMODE, 0x00020000,
976
977MX6_IOM_GRP_DDRPKE, 0x00000000,
978MX6_IOM_DRAM_SDBA2, 0x00000000,
979
980MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
981
982
983MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
984MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
985MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
986MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
987MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
988MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
989MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
990MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
991
992
993
994
995MX6_MMDC_P0_MDMISC, 0x00081740,
996
997
998
999
1000MX6_MMDC_P0_MDSCR, 0x00008000,
1001
1002
1003
1004MX6_MMDC_P0_MDPDC, 0x00020036,
1005MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1006MX6_MMDC_P0_MDCFG1, 0xff328f64,
1007MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1008MX6_MMDC_P0_MDRWD, 0x000026D2,
1009MX6_MMDC_P0_MDOR, 0x008E1023,
1010MX6_MMDC_P0_MDOTC, 0x09444040,
1011MX6_MMDC_P0_MDPDC, 0x00025576,
1012MX6_MMDC_P0_MDASP, 0x00000047,
1013MX6_MMDC_P0_MDCTL, 0x841A0000,
1014MX6_MMDC_P0_MDSCR, 0x02888032,
1015MX6_MMDC_P0_MDSCR, 0x00008033,
1016MX6_MMDC_P0_MDSCR, 0x00048031,
1017MX6_MMDC_P0_MDSCR, 0x19408030,
1018MX6_MMDC_P0_MDSCR, 0x04008040,
1019MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1020MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1021MX6_MMDC_P0_MDREF, 0x00007800,
1022MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1023MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1024
1025MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1026MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1027MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1028MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1029
1030MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1031MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1032
1033MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1034MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1035
1036MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1037MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1038MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1039MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1040
1041MX6_MMDC_P0_MPMUR0, 0x00000800,
1042MX6_MMDC_P1_MPMUR0, 0x00000800,
1043MX6_MMDC_P0_MDSCR, 0x00000000,
1044MX6_MMDC_P0_MAPSR, 0x00011006,
1045};
1046
1047static void ccgr_init(void)
1048{
1049 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1050
1051 writel(0x00C03F3F, &ccm->CCGR0);
1052 writel(0x0030FC03, &ccm->CCGR1);
1053 writel(0x0FFFFFF3, &ccm->CCGR2);
1054 writel(0x3FF0300F, &ccm->CCGR3);
1055 writel(0x00FFF300, &ccm->CCGR4);
1056 writel(0x0F0000F3, &ccm->CCGR5);
1057 writel(0x000003FF, &ccm->CCGR6);
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068 writel(0x000000FB, &ccm->ccosr);
1069}
1070
1071static void ddr_init(int *table, int size)
1072{
1073 int i;
1074
1075 for (i = 0; i < size / 2 ; i++)
1076 writel(table[2 * i + 1], table[2 * i]);
1077}
1078
1079
1080static void spl_dram_perform_cal(void)
1081{
1082#ifdef CONFIG_MX6_DDRCAL
1083 int err;
1084 struct mx6_ddr_sysinfo ddr_sysinfo = {
1085 .dsize = 2,
1086 };
1087
1088 err = mmdc_do_write_level_calibration(&ddr_sysinfo);
1089 if (err)
1090 printf("error %d from write level calibration\n", err);
1091 err = mmdc_do_dqs_calibration(&ddr_sysinfo);
1092 if (err)
1093 printf("error %d from dqs calibration\n", err);
1094#endif
1095}
1096
1097static void spl_dram_init(void)
1098{
1099 int minc, maxc;
1100
1101 switch (get_cpu_temp_grade(&minc, &maxc)) {
1102 case TEMP_COMMERCIAL:
1103 case TEMP_EXTCOMMERCIAL:
1104 puts("Commercial temperature grade DDR3 timings.\n");
1105 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1106 break;
1107 case TEMP_INDUSTRIAL:
1108 case TEMP_AUTOMOTIVE:
1109 default:
1110 puts("Industrial temperature grade DDR3 timings.\n");
1111 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1112 break;
1113 };
1114 udelay(100);
1115 spl_dram_perform_cal();
1116}
1117
1118void board_init_f(ulong dummy)
1119{
1120
1121 arch_cpu_init();
1122
1123 ccgr_init();
1124 gpr_init();
1125
1126
1127 board_early_init_f();
1128
1129
1130 timer_init();
1131
1132
1133 preloader_console_init();
1134
1135#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1136
1137 setup_dtemode_uart();
1138#endif
1139
1140
1141 spl_dram_init();
1142
1143
1144 memset(__bss_start, 0, __bss_end - __bss_start);
1145
1146
1147 board_init_r(NULL, 0);
1148}
1149
1150#ifdef CONFIG_SPL_LOAD_FIT
1151int board_fit_config_name_match(const char *name)
1152{
1153 if (!strcmp(name, "imx6-apalis"))
1154 return 0;
1155
1156 return -1;
1157}
1158#endif
1159
1160void reset_cpu(void)
1161{
1162}
1163
1164#endif
1165
1166static struct mxc_serial_plat mxc_serial_plat = {
1167 .reg = (struct mxc_uart *)UART1_BASE,
1168 .use_dte = true,
1169};
1170
1171U_BOOT_DRVINFO(mxc_serial) = {
1172 .name = "serial_mxc",
1173 .plat = &mxc_serial_plat,
1174};
1175
