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6#include <common.h>
7#include <cpu.h>
8#include <dm.h>
9#include <thermal.h>
10#include <asm/global_data.h>
11#include <asm/system.h>
12#include <asm/arch/sci/sci.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/arch-imx/cpu.h>
15#include <asm/armv8/cpu.h>
16#include <linux/bitops.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20struct cpu_imx_plat {
21 const char *name;
22 const char *rev;
23 const char *type;
24 u32 cpu_rsrc;
25 u32 cpurev;
26 u32 freq_mhz;
27 u32 mpidr;
28};
29
30const char *get_imx8_type(u32 imxtype)
31{
32 switch (imxtype) {
33 case MXC_CPU_IMX8QXP:
34 case MXC_CPU_IMX8QXP_A0:
35 return "QXP";
36 case MXC_CPU_IMX8QM:
37 return "QM";
38 default:
39 return "??";
40 }
41}
42
43const char *get_imx8_rev(u32 rev)
44{
45 switch (rev) {
46 case CHIP_REV_A:
47 return "A";
48 case CHIP_REV_B:
49 return "B";
50 case CHIP_REV_C:
51 return "C";
52 default:
53 return "?";
54 }
55}
56
57static void set_core_data(struct udevice *dev)
58{
59 struct cpu_imx_plat *plat = dev_get_plat(dev);
60
61 if (device_is_compatible(dev, "arm,cortex-a35")) {
62 plat->cpu_rsrc = SC_R_A35;
63 plat->name = "A35";
64 } else if (device_is_compatible(dev, "arm,cortex-a53")) {
65 plat->cpu_rsrc = SC_R_A53;
66 plat->name = "A53";
67 } else if (device_is_compatible(dev, "arm,cortex-a72")) {
68 plat->cpu_rsrc = SC_R_A72;
69 plat->name = "A72";
70 } else {
71 plat->cpu_rsrc = SC_R_A53;
72 plat->name = "?";
73 }
74}
75
76#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
77static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
78{
79 struct udevice *thermal_dev;
80 int cpu_tmp, ret;
81 int idx = 1;
82
83 if (plat->cpu_rsrc == SC_R_A72)
84 idx = 2;
85
86 ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
87 if (!ret) {
88 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
89 if (ret)
90 return 0xdeadbeef;
91 } else {
92 return 0xdeadbeef;
93 }
94
95 return cpu_tmp;
96}
97#else
98static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
99{
100 return 0;
101}
102#endif
103
104int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
105{
106 struct cpu_imx_plat *plat = dev_get_plat(dev);
107 int ret, temp;
108
109 if (size < 100)
110 return -ENOSPC;
111
112 ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
113 plat->type, plat->rev, plat->name, plat->freq_mhz);
114
115 if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
116 temp = cpu_imx_get_temp(plat);
117 buf = buf + ret;
118 size = size - ret;
119 if (temp != 0xdeadbeef)
120 ret = snprintf(buf, size, " at %dC", temp);
121 else
122 ret = snprintf(buf, size, " - invalid sensor data");
123 }
124
125 snprintf(buf + ret, size - ret, "\n");
126
127 return 0;
128}
129
130static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
131{
132 struct cpu_imx_plat *plat = dev_get_plat(dev);
133
134 info->cpu_freq = plat->freq_mhz * 1000;
135 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
136 return 0;
137}
138
139static int cpu_imx_get_count(const struct udevice *dev)
140{
141 ofnode node;
142 int num = 0;
143
144 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
145 const char *device_type;
146
147 if (!ofnode_is_available(node))
148 continue;
149
150 device_type = ofnode_read_string(node, "device_type");
151 if (!device_type)
152 continue;
153
154 if (!strcmp(device_type, "cpu"))
155 num++;
156 }
157
158 return num;
159}
160
161static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
162{
163 snprintf(buf, size, "NXP");
164 return 0;
165}
166
167static int cpu_imx_is_current(struct udevice *dev)
168{
169 struct cpu_imx_plat *plat = dev_get_plat(dev);
170
171 if (plat->mpidr == (read_mpidr() & 0xffff))
172 return 1;
173
174 return 0;
175}
176
177static const struct cpu_ops cpu_imx8_ops = {
178 .get_desc = cpu_imx_get_desc,
179 .get_info = cpu_imx_get_info,
180 .get_count = cpu_imx_get_count,
181 .get_vendor = cpu_imx_get_vendor,
182 .is_current = cpu_imx_is_current,
183};
184
185static const struct udevice_id cpu_imx8_ids[] = {
186 { .compatible = "arm,cortex-a35" },
187 { .compatible = "arm,cortex-a53" },
188 { .compatible = "arm,cortex-a72" },
189 { }
190};
191
192static ulong imx8_get_cpu_rate(struct udevice *dev)
193{
194 struct cpu_imx_plat *plat = dev_get_plat(dev);
195 ulong rate;
196 int ret;
197
198 ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
199 (sc_pm_clock_rate_t *)&rate);
200 if (ret) {
201 printf("Could not read CPU frequency: %d\n", ret);
202 return 0;
203 }
204
205 return rate;
206}
207
208static int imx8_cpu_probe(struct udevice *dev)
209{
210 struct cpu_imx_plat *plat = dev_get_plat(dev);
211 u32 cpurev;
212
213 set_core_data(dev);
214 cpurev = get_cpu_rev();
215 plat->cpurev = cpurev;
216 plat->rev = get_imx8_rev(cpurev & 0xFFF);
217 plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
218 plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
219 plat->mpidr = dev_read_addr(dev);
220 if (plat->mpidr == FDT_ADDR_T_NONE) {
221 printf("%s: Failed to get CPU reg property\n", __func__);
222 return -EINVAL;
223 }
224
225 return 0;
226}
227
228U_BOOT_DRIVER(cpu_imx8_drv) = {
229 .name = "imx8x_cpu",
230 .id = UCLASS_CPU,
231 .of_match = cpu_imx8_ids,
232 .ops = &cpu_imx8_ops,
233 .probe = imx8_cpu_probe,
234 .plat_auto = sizeof(struct cpu_imx_plat),
235 .flags = DM_FLAG_PRE_RELOC,
236};
237
