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6#define LOG_CATEGORY UCLASS_GPIO
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <fdtdec.h>
12#include <log.h>
13#include <p2sb.h>
14#include <pch.h>
15#include <pci.h>
16#include <syscon.h>
17#include <acpi/acpi_device.h>
18#include <asm/cpu.h>
19#include <asm/gpio.h>
20#include <asm/intel_pinctrl.h>
21#include <asm/intel_pinctrl_defs.h>
22#include <asm/io.h>
23#include <asm/pci.h>
24#include <asm/arch/gpio.h>
25#include <dm/acpi.h>
26#include <dm/device-internal.h>
27#include <dt-bindings/gpio/x86-gpio.h>
28
29static int intel_gpio_get_value(struct udevice *dev, uint offset)
30{
31 struct udevice *pinctrl = dev_get_parent(dev);
32 uint mode, rx_tx;
33 u32 reg;
34
35 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
36 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
37 if (!mode) {
38 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
39 if (rx_tx == PAD_CFG0_TX_DISABLE)
40 return reg & PAD_CFG0_RX_STATE ? 1 : 0;
41 else if (rx_tx == PAD_CFG0_RX_DISABLE)
42 return reg & PAD_CFG0_TX_STATE ? 1 : 0;
43 }
44
45 return 0;
46}
47
48static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
49 int value)
50{
51 struct udevice *pinctrl = dev_get_parent(dev);
52 uint config_offset;
53
54 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
55
56 pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
57 value ? PAD_CFG0_TX_STATE : 0);
58
59 return 0;
60}
61
62static int intel_gpio_get_function(struct udevice *dev, uint offset)
63{
64 struct udevice *pinctrl = dev_get_parent(dev);
65 uint mode, rx_tx;
66 u32 reg;
67
68 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
69 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
70 if (!mode) {
71 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
72 if (rx_tx == PAD_CFG0_TX_DISABLE)
73 return GPIOF_INPUT;
74 else if (rx_tx == PAD_CFG0_RX_DISABLE)
75 return GPIOF_OUTPUT;
76 }
77
78 return GPIOF_FUNC;
79}
80
81static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
82 struct ofnode_phandle_args *args)
83{
84 struct udevice *pinctrl, *dev;
85 int gpio, ret;
86
87
88
89
90
91 gpio = args->args[0];
92 ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
93 if (ret)
94 return log_msg_ret("bad", ret);
95 device_find_first_child(pinctrl, &dev);
96 if (!dev)
97 return log_msg_ret("no child", -ENOENT);
98 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
99 desc->dev = dev;
100
101
102
103
104
105
106 if (orig_dev != dev) {
107 ret = device_probe(dev);
108 if (ret)
109 return log_msg_ret("probe", ret);
110 }
111
112 return 0;
113}
114
115static int intel_gpio_set_flags(struct udevice *dev, unsigned int offset,
116 ulong flags)
117{
118 struct udevice *pinctrl = dev_get_parent(dev);
119 u32 bic0 = 0, bic1 = 0;
120 u32 or0, or1;
121 uint config_offset;
122
123 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
124
125 if (flags & GPIOD_IS_OUT) {
126 bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
127 PAD_CFG0_TX_DISABLE;
128 or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE;
129 } else if (flags & GPIOD_IS_IN) {
130 bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
131 PAD_CFG0_RX_DISABLE;
132 or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE;
133 }
134 if (flags & GPIOD_PULL_UP) {
135 bic1 |= PAD_CFG1_PULL_MASK;
136 or1 |= PAD_CFG1_PULL_UP_20K;
137 } else if (flags & GPIOD_PULL_DOWN) {
138 bic1 |= PAD_CFG1_PULL_MASK;
139 or1 |= PAD_CFG1_PULL_DN_20K;
140 }
141
142 pcr_clrsetbits32(pinctrl, PAD_CFG0_OFFSET(config_offset), bic0, or0);
143 pcr_clrsetbits32(pinctrl, PAD_CFG1_OFFSET(config_offset), bic1, or1);
144 log_debug("%s: flags=%lx, offset=%x, config_offset=%x, %x/%x %x/%x\n",
145 dev->name, flags, offset, config_offset, bic0, or0, bic1, or1);
146
147 return 0;
148}
149
150#if CONFIG_IS_ENABLED(ACPIGEN)
151static int intel_gpio_get_acpi(const struct gpio_desc *desc,
152 struct acpi_gpio *gpio)
153{
154 struct udevice *pinctrl;
155 int ret;
156
157 if (!dm_gpio_is_valid(desc))
158 return -ENOENT;
159 pinctrl = dev_get_parent(desc->dev);
160
161 memset(gpio, '\0', sizeof(*gpio));
162
163 gpio->type = ACPI_GPIO_TYPE_IO;
164 gpio->pull = ACPI_GPIO_PULL_DEFAULT;
165 gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
166 gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
167 gpio->pin_count = 1;
168 gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
169 gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
170 desc->offset);
171 ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
172 if (ret)
173 return log_msg_ret("resource", ret);
174
175 return 0;
176}
177#endif
178
179static int intel_gpio_probe(struct udevice *dev)
180{
181 return 0;
182}
183
184static int intel_gpio_of_to_plat(struct udevice *dev)
185{
186 struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
187 struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
188 const struct pad_community *comm = pinctrl_priv->comm;
189
190 upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
191 upriv->bank_name = dev->name;
192
193 return 0;
194}
195
196static const struct dm_gpio_ops gpio_intel_ops = {
197 .get_value = intel_gpio_get_value,
198 .set_value = intel_gpio_set_value,
199 .get_function = intel_gpio_get_function,
200 .xlate = intel_gpio_xlate,
201 .set_flags = intel_gpio_set_flags,
202#if CONFIG_IS_ENABLED(ACPIGEN)
203 .get_acpi = intel_gpio_get_acpi,
204#endif
205};
206
207#if CONFIG_IS_ENABLED(OF_REAL)
208static const struct udevice_id intel_intel_gpio_ids[] = {
209 { .compatible = "intel,gpio" },
210 { }
211};
212#endif
213
214U_BOOT_DRIVER(intel_gpio) = {
215 .name = "intel_gpio",
216 .id = UCLASS_GPIO,
217 .of_match = of_match_ptr(intel_intel_gpio_ids),
218 .ops = &gpio_intel_ops,
219 .of_to_plat = intel_gpio_of_to_plat,
220 .probe = intel_gpio_probe,
221};
222