LXR uboot/drivers/net/dc2114x.c

   1// SPDX-License-Identifier: GPL-2.0+
   2
   3#include <common.h>
   4#include <asm/io.h>
   5#include <dm.h>
   6#include <malloc.h>
   7#include <net.h>
   8#include <netdev.h>
   9#include <pci.h>
  10#include <linux/bitops.h>
  11#include <linux/delay.h>
  12
  13#define SROM_DLEVEL     0
  14
  15/* PCI Registers. */
  16#define PCI_CFDA_PSM    0x43
  17
  18#define CFRV_RN         0x000000f0      /* Revision Number */
  19
  20#define WAKEUP          0x00            /* Power Saving Wakeup */
  21#define SLEEP           0x80            /* Power Saving Sleep Mode */
  22
  23#define DC2114x_BRK     0x0020  /* CFRV break between DC21142 & DC21143 */
  24
  25/* Ethernet chip registers. */
  26#define DE4X5_BMR       0x000           /* Bus Mode Register */
  27#define DE4X5_TPD       0x008           /* Transmit Poll Demand Reg */
  28#define DE4X5_RRBA      0x018           /* RX Ring Base Address Reg */
  29#define DE4X5_TRBA      0x020           /* TX Ring Base Address Reg */
  30#define DE4X5_STS       0x028           /* Status Register */
  31#define DE4X5_OMR       0x030           /* Operation Mode Register */
  32#define DE4X5_SICR      0x068           /* SIA Connectivity Register */
  33#define DE4X5_APROM     0x048           /* Ethernet Address PROM */
  34
  35/* Register bits. */
  36#define BMR_SWR         0x00000001      /* Software Reset */
  37#define STS_TS          0x00700000      /* Transmit Process State */
  38#define STS_RS          0x000e0000      /* Receive Process State */
  39#define OMR_ST          0x00002000      /* Start/Stop Transmission Command */
  40#define OMR_SR          0x00000002      /* Start/Stop Receive */
  41#define OMR_PS          0x00040000      /* Port Select */
  42#define OMR_SDP         0x02000000      /* SD Polarity - MUST BE ASSERTED */
  43#define OMR_PM          0x00000080      /* Pass All Multicast */
  44
  45/* Descriptor bits. */
  46#define R_OWN           0x80000000      /* Own Bit */
  47#define RD_RER          0x02000000      /* Receive End Of Ring */
  48#define RD_LS           0x00000100      /* Last Descriptor */
  49#define RD_ES           0x00008000      /* Error Summary */
  50#define TD_TER          0x02000000      /* Transmit End Of Ring */
  51#define T_OWN           0x80000000      /* Own Bit */
  52#define TD_LS           0x40000000      /* Last Segment */
  53#define TD_FS           0x20000000      /* First Segment */
  54#define TD_ES           0x00008000      /* Error Summary */
  55#define TD_SET          0x08000000      /* Setup Packet */
  56
  57/* The EEPROM commands include the alway-set leading bit. */
  58#define SROM_WRITE_CMD  5
  59#define SROM_READ_CMD   6
  60#define SROM_ERASE_CMD  7
  61
  62#define SROM_HWADD      0x0014          /* Hardware Address offset in SROM */
  63#define SROM_RD         0x00004000      /* Read from Boot ROM */
  64#define EE_DATA_WRITE   0x04            /* EEPROM chip data in. */
  65#define EE_WRITE_0      0x4801
  66#define EE_WRITE_1      0x4805
  67#define EE_DATA_READ    0x08            /* EEPROM chip data out. */
  68#define SROM_SR         0x00000800      /* Select Serial ROM when set */
  69
  70#define DT_IN           0x00000004      /* Serial Data In */
  71#define DT_CLK          0x00000002      /* Serial ROM Clock */
  72#define DT_CS           0x00000001      /* Serial ROM Chip Select */
  73
  74#define POLL_DEMAND     1
  75
  76#if defined(CONFIG_DM_ETH)
  77#define phys_to_bus(dev, a)     dm_pci_phys_to_mem((dev), (a))
  78#elif defined(CONFIG_E500)
  79#define phys_to_bus(dev, a)     (a)
  80#else
  81#define phys_to_bus(dev, a)     pci_phys_to_mem((dev), (a))
  82#endif
  83
  84#define NUM_RX_DESC PKTBUFSRX
  85#define NUM_TX_DESC 1                   /* Number of TX descriptors   */
  86#define RX_BUFF_SZ  PKTSIZE_ALIGN
  87
  88#define TOUT_LOOP   1000000
  89
  90#define SETUP_FRAME_LEN 192
  91
  92struct de4x5_desc {
  93        volatile s32 status;
  94        u32 des1;
  95        u32 buf;
  96        u32 next;
  97};
  98
  99struct dc2114x_priv {
 100        struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
 101        struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
 102        int rx_new;     /* RX descriptor ring pointer */
 103        int tx_new;     /* TX descriptor ring pointer */
 104        char rx_ring_size;
 105        char tx_ring_size;
 106#ifdef CONFIG_DM_ETH
 107        struct udevice          *devno;
 108#else
 109        struct eth_device       dev;
 110        pci_dev_t               devno;
 111#endif
 112        char                    *name;
 113        void __iomem            *iobase;
 114        u8                      *enetaddr;
 115};
 116
 117/* RX and TX descriptor ring */
 118static u32 dc2114x_inl(struct dc2114x_priv *priv, u32 addr)
 119{
 120        return le32_to_cpu(readl(priv->iobase + addr));
 121}
 122
 123static void dc2114x_outl(struct dc2114x_priv *priv, u32 command, u32 addr)
 124{
 125        writel(cpu_to_le32(command), priv->iobase + addr);
 126}
 127
 128static void reset_de4x5(struct dc2114x_priv *priv)
 129{
 130        u32 i;
 131
 132        i = dc2114x_inl(priv, DE4X5_BMR);
 133        mdelay(1);
 134        dc2114x_outl(priv, i | BMR_SWR, DE4X5_BMR);
 135        mdelay(1);
 136        dc2114x_outl(priv, i, DE4X5_BMR);
 137        mdelay(1);
 138
 139        for (i = 0; i < 5; i++) {
 140                dc2114x_inl(priv, DE4X5_BMR);
 141                mdelay(10);
 142        }
 143
 144        mdelay(1);
 145}
 146
 147static void start_de4x5(struct dc2114x_priv *priv)
 148{
 149        u32 omr;
 150
 151        omr = dc2114x_inl(priv, DE4X5_OMR);
 152        omr |= OMR_ST | OMR_SR;
 153        dc2114x_outl(priv, omr, DE4X5_OMR);     /* Enable the TX and/or RX */
 154}
 155
 156static void stop_de4x5(struct dc2114x_priv *priv)
 157{
 158        u32 omr;
 159
 160        omr = dc2114x_inl(priv, DE4X5_OMR);
 161        omr &= ~(OMR_ST | OMR_SR);
 162        dc2114x_outl(priv, omr, DE4X5_OMR);     /* Disable the TX and/or RX */
 163}
 164
 165/* SROM Read and write routines. */
 166static void sendto_srom(struct dc2114x_priv *priv, u_int command, u_long addr)
 167{
 168        dc2114x_outl(priv, command, addr);
 169        udelay(1);
 170}
 171
 172static int getfrom_srom(struct dc2114x_priv *priv, u_long addr)
 173{
 174        u32 tmp = dc2114x_inl(priv, addr);
 175
 176        udelay(1);
 177        return tmp;
 178}
 179
 180/* Note: this routine returns extra data bits for size detection. */
 181static int do_read_eeprom(struct dc2114x_priv *priv, u_long ioaddr, int location,
 182                          int addr_len)
 183{
 184        int read_cmd = location | (SROM_READ_CMD << addr_len);
 185        unsigned int retval = 0;
 186        int i;
 187
 188        sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
 189        sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
 190
 191        debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
 192
 193        /* Shift the read command bits out. */
 194        for (i = 4 + addr_len; i >= 0; i--) {
 195                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 196
 197                sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval,
 198                            ioaddr);
 199                udelay(10);
 200                sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
 201                            ioaddr);
 202                udelay(10);
 203                debug_cond(SROM_DLEVEL >= 2, "%X",
 204                           getfrom_srom(priv, ioaddr) & 15);
 205                retval = (retval << 1) |
 206                         !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
 207        }
 208
 209        sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
 210
 211        debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(priv, ioaddr) & 15);
 212
 213        for (i = 16; i > 0; i--) {
 214                sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 215                udelay(10);
 216                debug_cond(SROM_DLEVEL >= 2, "%X",
 217                           getfrom_srom(priv, ioaddr) & 15);
 218                retval = (retval << 1) |
 219                         !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
 220                sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
 221                udelay(10);
 222        }
 223
 224        /* Terminate the EEPROM access. */
 225        sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
 226
 227        debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
 228                   location, retval);
 229
 230        return retval;
 231}
 232
 233/*
 234 * This executes a generic EEPROM command, typically a write or write
 235 * enable. It returns the data output from the EEPROM, and thus may
 236 * also be used for reads.
 237 */
 238static int do_eeprom_cmd(struct dc2114x_priv *priv, u_long ioaddr, int cmd,
 239                         int cmd_len)
 240{
 241        unsigned int retval = 0;
 242
 243        debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
 244
 245        sendto_srom(priv, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
 246
 247        /* Shift the command bits out. */
 248        do {
 249                short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
 250
 251                sendto_srom(priv, dataval, ioaddr);
 252                udelay(10);
 253
 254                debug_cond(SROM_DLEVEL >= 2, "%X",
 255                           getfrom_srom(priv, ioaddr) & 15);
 256
 257                sendto_srom(priv, dataval | DT_CLK, ioaddr);
 258                udelay(10);
 259                retval = (retval << 1) |
 260                         !!(getfrom_srom(priv, ioaddr) & EE_DATA_READ);
 261        } while (--cmd_len >= 0);
 262
 263        sendto_srom(priv, SROM_RD | SROM_SR | DT_CS, ioaddr);
 264
 265        /* Terminate the EEPROM access. */
 266        sendto_srom(priv, SROM_RD | SROM_SR, ioaddr);
 267
 268        debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
 269
 270        return retval;
 271}
 272
 273static int read_srom(struct dc2114x_priv *priv, u_long ioaddr, int index)
 274{
 275        int ee_addr_size;
 276
 277        ee_addr_size = (do_read_eeprom(priv, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
 278
 279        return do_eeprom_cmd(priv, ioaddr, 0xffff |
 280                             (((SROM_READ_CMD << ee_addr_size) | index) << 16),
 281                             3 + ee_addr_size + 16);
 282}
 283
 284static void send_setup_frame(struct dc2114x_priv *priv)
 285{
 286        char setup_frame[SETUP_FRAME_LEN];
 287        char *pa = &setup_frame[0];
 288        int i;
 289
 290        memset(pa, 0xff, SETUP_FRAME_LEN);
 291
 292        for (i = 0; i < ETH_ALEN; i++) {
 293                *(pa + (i & 1)) = priv->enetaddr[i];
 294                if (i & 0x01)
 295                        pa += 4;
 296        }
 297
 298        for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
 299                if (i < TOUT_LOOP)
 300                        continue;
 301
 302                printf("%s: tx error buffer not ready\n", priv->name);
 303                return;
 304        }
 305
 306        priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
 307                                                      (u32)&setup_frame[0]));
 308        priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
 309        priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
 310
 311        dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
 312
 313        for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
 314                if (i < TOUT_LOOP)
 315                        continue;
 316
 317                printf("%s: tx buffer not ready\n", priv->name);
 318                return;
 319        }
 320
 321        if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) != 0x7FFFFFFF) {
 322                printf("TX error status2 = 0x%08X\n",
 323                       le32_to_cpu(priv->tx_ring[priv->tx_new].status));
 324        }
 325
 326        priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
 327}
 328
 329static int dc21x4x_send_common(struct dc2114x_priv *priv, void *packet, int length)
 330{
 331        int status = -1;
 332        int i;
 333
 334        if (length <= 0) {
 335                printf("%s: bad packet size: %d\n", priv->name, length);
 336                goto done;
 337        }
 338
 339        for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
 340                if (i < TOUT_LOOP)
 341                        continue;
 342
 343                printf("%s: tx error buffer not ready\n", priv->name);
 344                goto done;
 345        }
 346
 347        priv->tx_ring[priv->tx_new].buf = cpu_to_le32(phys_to_bus(priv->devno,
 348                                                      (u32)packet));
 349        priv->tx_ring[priv->tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
 350        priv->tx_ring[priv->tx_new].status = cpu_to_le32(T_OWN);
 351
 352        dc2114x_outl(priv, POLL_DEMAND, DE4X5_TPD);
 353
 354        for (i = 0; priv->tx_ring[priv->tx_new].status & cpu_to_le32(T_OWN); i++) {
 355                if (i < TOUT_LOOP)
 356                        continue;
 357
 358                printf(".%s: tx buffer not ready\n", priv->name);
 359                goto done;
 360        }
 361
 362        if (le32_to_cpu(priv->tx_ring[priv->tx_new].status) & TD_ES) {
 363                priv->tx_ring[priv->tx_new].status = 0x0;
 364                goto done;
 365        }
 366
 367        status = length;
 368
 369done:
 370        priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
 371        return status;
 372}
 373
 374static int dc21x4x_recv_check(struct dc2114x_priv *priv)
 375{
 376        int length = 0;
 377        u32 status;
 378
 379        status = le32_to_cpu(priv->rx_ring[priv->rx_new].status);
 380
 381        if (status & R_OWN)
 382                return 0;
 383
 384        if (status & RD_LS) {
 385                /* Valid frame status. */
 386                if (status & RD_ES) {
 387                        /* There was an error. */
 388                        printf("RX error status = 0x%08X\n", status);
 389                        return -EINVAL;
 390                } else {
 391                        /* A valid frame received. */
 392                        length = (le32_to_cpu(priv->rx_ring[priv->rx_new].status)
 393                                  >> 16);
 394
 395                        return length;
 396                }
 397        }
 398
 399        return -EAGAIN;
 400}
 401
 402static int dc21x4x_init_common(struct dc2114x_priv *priv)
 403{
 404        int i;
 405
 406        reset_de4x5(priv);
 407
 408        if (dc2114x_inl(priv, DE4X5_STS) & (STS_TS | STS_RS)) {
 409                printf("Error: Cannot reset ethernet controller.\n");
 410                return -1;
 411        }
 412
 413        dc2114x_outl(priv, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
 414
 415        for (i = 0; i < NUM_RX_DESC; i++) {
 416                priv->rx_ring[i].status = cpu_to_le32(R_OWN);
 417                priv->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
 418                priv->rx_ring[i].buf = cpu_to_le32(phys_to_bus(priv->devno,
 419                                             (u32)net_rx_packets[i]));
 420                priv->rx_ring[i].next = 0;
 421        }
 422
 423        for (i = 0; i < NUM_TX_DESC; i++) {
 424                priv->tx_ring[i].status = 0;
 425                priv->tx_ring[i].des1 = 0;
 426                priv->tx_ring[i].buf = 0;
 427                priv->tx_ring[i].next = 0;
 428        }
 429
 430        priv->rx_ring_size = NUM_RX_DESC;
 431        priv->tx_ring_size = NUM_TX_DESC;
 432
 433        /* Write the end of list marker to the descriptor lists. */
 434        priv->rx_ring[priv->rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
 435        priv->tx_ring[priv->tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
 436
 437        /* Tell the adapter where the TX/RX rings are located. */
 438        dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->rx_ring),
 439                     DE4X5_RRBA);
 440        dc2114x_outl(priv, phys_to_bus(priv->devno, (u32)&priv->tx_ring),
 441                     DE4X5_TRBA);
 442
 443        start_de4x5(priv);
 444
 445        priv->tx_new = 0;
 446        priv->rx_new = 0;
 447
 448        send_setup_frame(priv);
 449
 450        return 0;
 451}
 452
 453static void dc21x4x_halt_common(struct dc2114x_priv *priv)
 454{
 455        stop_de4x5(priv);
 456        dc2114x_outl(priv, 0, DE4X5_SICR);
 457}
 458
 459static void read_hw_addr(struct dc2114x_priv *priv)
 460{
 461        u_short tmp, *p = (u_short *)(&priv->enetaddr[0]);
 462        int i, j = 0;
 463
 464        for (i = 0; i < (ETH_ALEN >> 1); i++) {
 465                tmp = read_srom(priv, DE4X5_APROM, (SROM_HWADD >> 1) + i);
 466                *p = le16_to_cpu(tmp);
 467                j += *p++;
 468        }
 469
 470        if (!j || j == 0x2fffd) {
 471                memset(priv->enetaddr, 0, ETH_ALEN);
 472                debug("Warning: can't read HW address from SROM.\n");
 473        }
 474}
 475
 476static struct pci_device_id supported[] = {
 477        { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST) },
 478        { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142) },
 479        { }
 480};
 481
 482#ifndef CONFIG_DM_ETH
 483static int dc21x4x_init(struct eth_device *dev, struct bd_info *bis)
 484{
 485        struct dc2114x_priv *priv =
 486                container_of(dev, struct dc2114x_priv, dev);
 487
 488        /* Ensure we're not sleeping. */
 489        pci_write_config_byte(priv->devno, PCI_CFDA_PSM, WAKEUP);
 490
 491        return dc21x4x_init_common(priv);
 492}
 493
 494static void dc21x4x_halt(struct eth_device *dev)
 495{
 496        struct dc2114x_priv *priv =
 497                container_of(dev, struct dc2114x_priv, dev);
 498
 499        dc21x4x_halt_common(priv);
 500
 501        pci_write_config_byte(priv->devno, PCI_CFDA_PSM, SLEEP);
 502}
 503
 504static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
 505{
 506        struct dc2114x_priv *priv =
 507                container_of(dev, struct dc2114x_priv, dev);
 508
 509        return dc21x4x_send_common(priv, packet, length);
 510}
 511
 512static int dc21x4x_recv(struct eth_device *dev)
 513{
 514        struct dc2114x_priv *priv =
 515                container_of(dev, struct dc2114x_priv, dev);
 516        int length = 0;
 517        int ret;
 518
 519        while (true) {
 520                ret = dc21x4x_recv_check(priv);
 521                if (!ret)
 522                        break;
 523
 524                if (ret > 0) {
 525                        length = ret;
 526                        /* Pass the packet up to the protocol layers */
 527                        net_process_received_packet
 528                                (net_rx_packets[priv->rx_new], length - 4);
 529                }
 530
 531                /*
 532                 * Change buffer ownership for this frame,
 533                 * back to the adapter.
 534                 */
 535                if (ret != -EAGAIN)
 536                        priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
 537
 538                /* Update entry information. */
 539                priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
 540        }
 541
 542        return length;
 543}
 544
 545int dc21x4x_initialize(struct bd_info *bis)
 546{
 547        struct dc2114x_priv *priv;
 548        struct eth_device *dev;
 549        unsigned short status;
 550        unsigned char timer;
 551        unsigned int iobase;
 552        int card_number = 0;
 553        pci_dev_t devbusfn;
 554        int idx = 0;
 555
 556        while (1) {
 557                devbusfn = pci_find_devices(supported, idx++);
 558                if (devbusfn == -1)
 559                        break;
 560
 561                pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 562                status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 563                pci_write_config_word(devbusfn, PCI_COMMAND, status);
 564
 565                pci_read_config_word(devbusfn, PCI_COMMAND, &status);
 566                if (!(status & PCI_COMMAND_MEMORY)) {
 567                        printf("Error: Can not enable MEMORY access.\n");
 568                        continue;
 569                }
 570
 571                if (!(status & PCI_COMMAND_MASTER)) {
 572                        printf("Error: Can not enable Bus Mastering.\n");
 573                        continue;
 574                }
 575
 576                /* Check the latency timer for values >= 0x60. */
 577                pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
 578
 579                if (timer < 0x60) {
 580                        pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
 581                                              0x60);
 582                }
 583
 584                /* read BAR for memory space access */
 585                pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
 586                iobase &= PCI_BASE_ADDRESS_MEM_MASK;
 587                debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
 588
 589                priv = memalign(32, sizeof(*priv));
 590                if (!priv) {
 591                        printf("Can not allocalte memory of dc21x4x\n");
 592                        break;
 593                }
 594                memset(priv, 0, sizeof(*priv));
 595
 596                dev = &priv->dev;
 597
 598                sprintf(dev->name, "dc21x4x#%d", card_number);
 599                priv->devno = devbusfn;
 600                priv->name = dev->name;
 601                priv->enetaddr = dev->enetaddr;
 602
 603                dev->iobase = pci_mem_to_phys(devbusfn, iobase);
 604                dev->priv = (void *)devbusfn;
 605                dev->init = dc21x4x_init;
 606                dev->halt = dc21x4x_halt;
 607                dev->send = dc21x4x_send;
 608                dev->recv = dc21x4x_recv;
 609
 610                /* Ensure we're not sleeping. */
 611                pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
 612
 613                udelay(10 * 1000);
 614
 615                read_hw_addr(priv);
 616
 617                eth_register(dev);
 618
 619                card_number++;
 620        }
 621
 622        return card_number;
 623}
 624
 625#else   /* DM_ETH */
 626static int dc2114x_start(struct udevice *dev)
 627{
 628        struct eth_pdata *plat = dev_get_plat(dev);
 629        struct dc2114x_priv *priv = dev_get_priv(dev);
 630
 631        memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
 632
 633        /* Ensure we're not sleeping. */
 634        dm_pci_write_config8(dev, PCI_CFDA_PSM, WAKEUP);
 635
 636        return dc21x4x_init_common(priv);
 637}
 638
 639static void dc2114x_stop(struct udevice *dev)
 640{
 641        struct dc2114x_priv *priv = dev_get_priv(dev);
 642
 643        dc21x4x_halt_common(priv);
 644
 645        dm_pci_write_config8(dev, PCI_CFDA_PSM, SLEEP);
 646}
 647
 648static int dc2114x_send(struct udevice *dev, void *packet, int length)
 649{
 650        struct dc2114x_priv *priv = dev_get_priv(dev);
 651        int ret;
 652
 653        ret = dc21x4x_send_common(priv, packet, length);
 654
 655        return ret ? 0 : -ETIMEDOUT;
 656}
 657
 658static int dc2114x_recv(struct udevice *dev, int flags, uchar **packetp)
 659{
 660        struct dc2114x_priv *priv = dev_get_priv(dev);
 661        int ret;
 662
 663        ret = dc21x4x_recv_check(priv);
 664
 665        if (ret < 0) {
 666                /* Update entry information. */
 667                priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
 668                ret = 0;
 669        }
 670
 671        if (!ret)
 672                return 0;
 673
 674        *packetp = net_rx_packets[priv->rx_new];
 675
 676        return ret - 4;
 677}
 678
 679static int dc2114x_free_pkt(struct udevice *dev, uchar *packet, int length)
 680{
 681        struct dc2114x_priv *priv = dev_get_priv(dev);
 682
 683        priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
 684
 685        /* Update entry information. */
 686        priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
 687
 688        return 0;
 689}
 690
 691static int dc2114x_read_rom_hwaddr(struct udevice *dev)
 692{
 693        struct dc2114x_priv *priv = dev_get_priv(dev);
 694
 695        read_hw_addr(priv);
 696
 697        return 0;
 698}
 699
 700static int dc2114x_bind(struct udevice *dev)
 701{
 702        static int card_number;
 703        char name[16];
 704
 705        sprintf(name, "dc2114x#%u", card_number++);
 706
 707        return device_set_name(dev, name);
 708}
 709
 710static int dc2114x_probe(struct udevice *dev)
 711{
 712        struct eth_pdata *plat = dev_get_plat(dev);
 713        struct dc2114x_priv *priv = dev_get_priv(dev);
 714        u16 command, status;
 715        u32 iobase;
 716
 717        dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
 718        iobase &= ~0xf;
 719
 720        debug("dc2114x: DEC 2114x PCI Device @0x%x\n", iobase);
 721
 722        priv->devno = dev;
 723        priv->enetaddr = plat->enetaddr;
 724        priv->iobase = (void __iomem *)dm_pci_mem_to_phys(dev, iobase);
 725
 726        command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 727        dm_pci_write_config16(dev, PCI_COMMAND, command);
 728        dm_pci_read_config16(dev, PCI_COMMAND, &status);
 729        if ((status & command) != command) {
 730                printf("dc2114x: Couldn't enable IO access or Bus Mastering\n");
 731                return -EINVAL;
 732        }
 733
 734        dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x60);
 735
 736        return 0;
 737}
 738
 739static const struct eth_ops dc2114x_ops = {
 740        .start          = dc2114x_start,
 741        .send           = dc2114x_send,
 742        .recv           = dc2114x_recv,
 743        .stop           = dc2114x_stop,
 744        .free_pkt       = dc2114x_free_pkt,
 745        .read_rom_hwaddr = dc2114x_read_rom_hwaddr,
 746};
 747
 748U_BOOT_DRIVER(eth_dc2114x) = {
 749        .name   = "eth_dc2114x",
 750        .id     = UCLASS_ETH,
 751        .bind   = dc2114x_bind,
 752        .probe  = dc2114x_probe,
 753        .ops    = &dc2114x_ops,
 754        .priv_auto      = sizeof(struct dc2114x_priv),
 755        .plat_auto      = sizeof(struct eth_pdata),
 756};
 757
 758U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
 759#endif
 760