LXR uboot/drivers/net/fm/memac

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2012 Freescale Semiconductor, Inc.
   4 *      Andy Fleming <afleming@gmail.com>
   5 *      Roy Zang <tie-fei.zang@freescale.com>
   6 * Some part is taken from tsec.c
   7 */
   8#include <common.h>
   9#include <miiphy.h>
  10#include <phy.h>
  11#include <asm/io.h>
  12#include <fsl_memac.h>
  13#include <fm_eth.h>
  14
  15#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  16#define memac_out_32(a, v)      out_le32(a, v)
  17#define memac_clrbits_32(a, v)  clrbits_le32(a, v)
  18#define memac_setbits_32(a, v)  setbits_le32(a, v)
  19#else
  20#define memac_out_32(a, v)      out_be32(a, v)
  21#define memac_clrbits_32(a, v)  clrbits_be32(a, v)
  22#define memac_setbits_32(a, v)  setbits_be32(a, v)
  23#endif
  24
  25#ifdef CONFIG_DM_ETH
  26struct fm_mdio_priv {
  27        struct memac_mdio_controller *regs;
  28};
  29#endif
  30
  31#define MAX_NUM_RETRIES         1000
  32
  33static u32 memac_in_32(u32 *reg)
  34{
  35#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
  36        return in_le32(reg);
  37#else
  38        return in_be32(reg);
  39#endif
  40}
  41
  42/*
  43 * Wait until the MDIO bus is free
  44 */
  45static int memac_wait_until_free(struct memac_mdio_controller *regs)
  46{
  47        unsigned int timeout = MAX_NUM_RETRIES;
  48
  49        while ((memac_in_32(&regs->mdio_stat) & MDIO_STAT_BSY) && timeout--)
  50                ;
  51
  52        if (!timeout) {
  53                printf("timeout waiting for MDIO bus to be free\n");
  54                return -ETIMEDOUT;
  55        }
  56
  57        return 0;
  58}
  59
  60/*
  61 * Wait till the MDIO read or write operation is complete
  62 */
  63static int memac_wait_until_done(struct memac_mdio_controller *regs)
  64{
  65        unsigned int timeout = MAX_NUM_RETRIES;
  66
  67        while ((memac_in_32(&regs->mdio_stat) & MDIO_STAT_BSY) && timeout--)
  68                ;
  69
  70        if (!timeout) {
  71                printf("timeout waiting for MDIO operation to complete\n");
  72                return -ETIMEDOUT;
  73        }
  74
  75        return 0;
  76}
  77
  78/*
  79 * Write value to the PHY for this device to the register at regnum, waiting
  80 * until the write is done before it returns.  All PHY configuration has to be
  81 * done through the TSEC1 MIIM regs
  82 */
  83int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
  84                        int regnum, u16 value)
  85{
  86        struct memac_mdio_controller *regs;
  87        u32 mdio_ctl;
  88        u32 c45 = 1; /* Default to 10G interface */
  89        int err;
  90
  91#ifndef CONFIG_DM_ETH
  92        regs = bus->priv;
  93#else
  94        struct fm_mdio_priv *priv;
  95
  96        if (!bus->priv)
  97                return -EINVAL;
  98        priv = dev_get_priv(bus->priv);
  99        regs = priv->regs;
 100        debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
 101              regs, port_addr, dev_addr, regnum, value);
 102#endif
 103
 104        if (dev_addr == MDIO_DEVAD_NONE) {
 105                c45 = 0; /* clause 22 */
 106                dev_addr = regnum & 0x1f;
 107                memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 108        } else
 109                memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 110
 111        err = memac_wait_until_free(regs);
 112        if (err)
 113                return err;
 114
 115        /* Set the port and dev addr */
 116        mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
 117        memac_out_32(&regs->mdio_ctl, mdio_ctl);
 118
 119        /* Set the register address */
 120        if (c45)
 121                memac_out_32(&regs->mdio_addr, regnum & 0xffff);
 122
 123        err = memac_wait_until_free(regs);
 124        if (err)
 125                return err;
 126
 127        /* Write the value to the register */
 128        memac_out_32(&regs->mdio_data, MDIO_DATA(value));
 129
 130        err = memac_wait_until_done(regs);
 131        if (err)
 132                return err;
 133
 134        return 0;
 135}
 136
 137/*
 138 * Reads from register regnum in the PHY for device dev, returning the value.
 139 * Clears miimcom first.  All PHY configuration has to be done through the
 140 * TSEC1 MIIM regs
 141 */
 142int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 143                        int regnum)
 144{
 145        struct memac_mdio_controller *regs;
 146        u32 mdio_ctl;
 147        u32 c45 = 1;
 148        int err;
 149
 150#ifndef CONFIG_DM_ETH
 151        regs = bus->priv;
 152#else
 153        struct fm_mdio_priv *priv;
 154
 155        if (!bus->priv)
 156                return -EINVAL;
 157        priv = dev_get_priv(bus->priv);
 158        regs = priv->regs;
 159#endif
 160
 161        if (dev_addr == MDIO_DEVAD_NONE) {
 162#ifndef CONFIG_DM_ETH
 163                if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
 164                        return 0xffff;
 165#endif
 166                c45 = 0; /* clause 22 */
 167                dev_addr = regnum & 0x1f;
 168                memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 169        } else
 170                memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
 171
 172        err = memac_wait_until_free(regs);
 173        if (err)
 174                return err;
 175
 176        /* Set the Port and Device Addrs */
 177        mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
 178        memac_out_32(&regs->mdio_ctl, mdio_ctl);
 179
 180        /* Set the register address */
 181        if (c45)
 182                memac_out_32(&regs->mdio_addr, regnum & 0xffff);
 183
 184        err = memac_wait_until_free(regs);
 185        if (err)
 186                return err;
 187
 188        /* Initiate the read */
 189        mdio_ctl |= MDIO_CTL_READ;
 190        memac_out_32(&regs->mdio_ctl, mdio_ctl);
 191
 192        err = memac_wait_until_done(regs);
 193        if (err)
 194                return err;
 195
 196        /* Return all Fs if nothing was there */
 197        if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
 198                return 0xffff;
 199
 200        return memac_in_32(&regs->mdio_data) & 0xffff;
 201}
 202
 203int memac_mdio_reset(struct mii_dev *bus)
 204{
 205        return 0;
 206}
 207
 208#ifndef CONFIG_DM_ETH
 209int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info)
 210{
 211        struct mii_dev *bus = mdio_alloc();
 212
 213        if (!bus) {
 214                printf("Failed to allocate FM TGEC MDIO bus\n");
 215                return -1;
 216        }
 217
 218        bus->read = memac_mdio_read;
 219        bus->write = memac_mdio_write;
 220        bus->reset = memac_mdio_reset;
 221        strcpy(bus->name, info->name);
 222
 223        bus->priv = info->regs;
 224
 225        /*
 226         * On some platforms like B4860, default value of MDIO_CLK_DIV bits
 227         * in mdio_stat(mdio_cfg) register generates MDIO clock too high
 228         * (much higher than 2.5MHz), violating the IEEE specs.
 229         * On other platforms like T1040, default value of MDIO_CLK_DIV bits
 230         * is zero, so MDIO clock is disabled.
 231         * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
 232         * be properly initialized.
 233         * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
 234         * like T2080QDS, this bit default is '0', which leads to MDIO failure
 235         * on XAUI PHY, so set this bit definitely.
 236         */
 237        memac_setbits_32(
 238                &((struct memac_mdio_controller *)info->regs)->mdio_stat,
 239                MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
 240
 241        return mdio_register(bus);
 242}
 243
 244#else /* CONFIG_DM_ETH */
 245#if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
 246static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
 247{
 248        struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
 249                                                 NULL;
 250
 251        if (pdata && pdata->mii_bus)
 252                return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
 253
 254        return -1;
 255}
 256
 257static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
 258                         u16 val)
 259{
 260        struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
 261                                                 NULL;
 262
 263        if (pdata && pdata->mii_bus)
 264                return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
 265
 266        return -1;
 267}
 268
 269static int fm_mdio_reset(struct udevice *dev)
 270{
 271        struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
 272                                                 NULL;
 273
 274        if (pdata && pdata->mii_bus)
 275                return memac_mdio_reset(pdata->mii_bus);
 276
 277        return -1;
 278}
 279
 280static const struct mdio_ops fm_mdio_ops = {
 281        .read = fm_mdio_read,
 282        .write = fm_mdio_write,
 283        .reset = fm_mdio_reset,
 284};
 285
 286static const struct udevice_id fm_mdio_ids[] = {
 287        { .compatible = "fsl,fman-memac-mdio" },
 288        {}
 289};
 290
 291static int fm_mdio_probe(struct udevice *dev)
 292{
 293        struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
 294        struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
 295                                                 NULL;
 296
 297        if (!dev) {
 298                printf("%s dev = NULL\n", __func__);
 299                return -1;
 300        }
 301        if (!priv) {
 302                printf("dev_get_priv(dev %p) = NULL\n", dev);
 303                return -1;
 304        }
 305        priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
 306        debug("%s priv %p @ regs %p, pdata %p\n", __func__,
 307              priv, priv->regs, pdata);
 308
 309        /*
 310         * On some platforms like B4860, default value of MDIO_CLK_DIV bits
 311         * in mdio_stat(mdio_cfg) register generates MDIO clock too high
 312         * (much higher than 2.5MHz), violating the IEEE specs.
 313         * On other platforms like T1040, default value of MDIO_CLK_DIV bits
 314         * is zero, so MDIO clock is disabled.
 315         * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
 316         * be properly initialized.
 317         * The default NEG bit should be '1' as per FMANv3 RM, but on platforms
 318         * like T2080QDS, this bit default is '0', which leads to MDIO failure
 319         * on XAUI PHY, so set this bit definitely.
 320         */
 321        if (priv && priv->regs && priv->regs->mdio_stat)
 322                memac_setbits_32(&priv->regs->mdio_stat,
 323                                 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
 324
 325        return 0;
 326}
 327
 328static int fm_mdio_remove(struct udevice *dev)
 329{
 330        return 0;
 331}
 332
 333U_BOOT_DRIVER(fman_mdio) = {
 334        .name = "fman_mdio",
 335        .id = UCLASS_MDIO,
 336        .of_match = fm_mdio_ids,
 337        .probe = fm_mdio_probe,
 338        .remove = fm_mdio_remove,
 339        .ops = &fm_mdio_ops,
 340        .priv_auto      = sizeof(struct fm_mdio_priv),
 341        .plat_auto      = sizeof(struct mdio_perdev_priv),
 342};
 343#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
 344#endif /* CONFIG_DM_ETH */
 345