1
2
3
4
5
6
7
8
9
10
11
12#define pr_fmt(fmt) "tegra-pcie: " fmt
13
14#include <common.h>
15#include <clk.h>
16#include <dm.h>
17#include <errno.h>
18#include <log.h>
19#include <malloc.h>
20#include <pci.h>
21#include <pci_tegra.h>
22#include <power-domain.h>
23#include <reset.h>
24#include <linux/delay.h>
25
26#include <asm/io.h>
27#include <asm/gpio.h>
28
29#include <linux/ioport.h>
30#include <linux/list.h>
31
32#ifndef CONFIG_TEGRA186
33#include <asm/arch/clock.h>
34#include <asm/arch/powergate.h>
35#include <asm/arch-tegra/xusb-padctl.h>
36#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
37#endif
38
39
40
41
42
43
44
45
46
47
48#define AFI_AXI_BAR0_SZ 0x00
49#define AFI_AXI_BAR1_SZ 0x04
50#define AFI_AXI_BAR2_SZ 0x08
51#define AFI_AXI_BAR3_SZ 0x0c
52#define AFI_AXI_BAR4_SZ 0x10
53#define AFI_AXI_BAR5_SZ 0x14
54
55#define AFI_AXI_BAR0_START 0x18
56#define AFI_AXI_BAR1_START 0x1c
57#define AFI_AXI_BAR2_START 0x20
58#define AFI_AXI_BAR3_START 0x24
59#define AFI_AXI_BAR4_START 0x28
60#define AFI_AXI_BAR5_START 0x2c
61
62#define AFI_FPCI_BAR0 0x30
63#define AFI_FPCI_BAR1 0x34
64#define AFI_FPCI_BAR2 0x38
65#define AFI_FPCI_BAR3 0x3c
66#define AFI_FPCI_BAR4 0x40
67#define AFI_FPCI_BAR5 0x44
68
69#define AFI_CACHE_BAR0_SZ 0x48
70#define AFI_CACHE_BAR0_ST 0x4c
71#define AFI_CACHE_BAR1_SZ 0x50
72#define AFI_CACHE_BAR1_ST 0x54
73
74#define AFI_MSI_BAR_SZ 0x60
75#define AFI_MSI_FPCI_BAR_ST 0x64
76#define AFI_MSI_AXI_BAR_ST 0x68
77
78#define AFI_CONFIGURATION 0xac
79#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
80
81#define AFI_FPCI_ERROR_MASKS 0xb0
82
83#define AFI_INTR_MASK 0xb4
84#define AFI_INTR_MASK_INT_MASK (1 << 0)
85#define AFI_INTR_MASK_MSI_MASK (1 << 8)
86
87#define AFI_SM_INTR_ENABLE 0xc4
88#define AFI_SM_INTR_INTA_ASSERT (1 << 0)
89#define AFI_SM_INTR_INTB_ASSERT (1 << 1)
90#define AFI_SM_INTR_INTC_ASSERT (1 << 2)
91#define AFI_SM_INTR_INTD_ASSERT (1 << 3)
92#define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
93#define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
94#define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
95#define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
96
97#define AFI_AFI_INTR_ENABLE 0xc8
98#define AFI_INTR_EN_INI_SLVERR (1 << 0)
99#define AFI_INTR_EN_INI_DECERR (1 << 1)
100#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
101#define AFI_INTR_EN_TGT_DECERR (1 << 3)
102#define AFI_INTR_EN_TGT_WRERR (1 << 4)
103#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
104#define AFI_INTR_EN_AXI_DECERR (1 << 6)
105#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
106#define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
107
108#define AFI_PCIE_CONFIG 0x0f8
109#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
110#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
111#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
112#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
113#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
114#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
115#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
117#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
118#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
119#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
120#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
121#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
122
123#define AFI_FUSE 0x104
124#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
125
126#define AFI_PEX0_CTRL 0x110
127#define AFI_PEX1_CTRL 0x118
128#define AFI_PEX2_CTRL 0x128
129#define AFI_PEX2_CTRL_T186 0x19c
130#define AFI_PEX_CTRL_RST (1 << 0)
131#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
132#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
133#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
134
135#define AFI_PLLE_CONTROL 0x160
136#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
137#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
138
139#define AFI_PEXBIAS_CTRL_0 0x168
140
141#define PADS_CTL_SEL 0x0000009C
142
143#define PADS_CTL 0x000000A0
144#define PADS_CTL_IDDQ_1L (1 << 0)
145#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
146#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
147
148#define PADS_PLL_CTL_TEGRA20 0x000000B8
149#define PADS_PLL_CTL_TEGRA30 0x000000B4
150#define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
151#define PADS_PLL_CTL_LOCKDET (0x1 << 8)
152#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
153#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
154#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
155#define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
156#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
157#define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
158#define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
159#define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
160
161#define PADS_REFCLK_CFG0 0x000000C8
162#define PADS_REFCLK_CFG1 0x000000CC
163
164
165
166
167
168
169#define PADS_REFCLK_CFG_TERM_SHIFT 2
170#define PADS_REFCLK_CFG_E_TERM_SHIFT 7
171#define PADS_REFCLK_CFG_PREDI_SHIFT 8
172#define PADS_REFCLK_CFG_DRVI_SHIFT 12
173
174#define RP_VEND_XP 0x00000F00
175#define RP_VEND_XP_DL_UP (1 << 30)
176
177#define RP_VEND_CTL2 0x00000FA8
178#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
179
180#define RP_PRIV_MISC 0x00000FE0
181#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
182#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
183
184#define RP_LINK_CONTROL_STATUS 0x00000090
185#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
186#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
187
188enum tegra_pci_id {
189 TEGRA20_PCIE,
190 TEGRA30_PCIE,
191 TEGRA124_PCIE,
192 TEGRA210_PCIE,
193 TEGRA186_PCIE,
194};
195
196struct tegra_pcie_port {
197 struct tegra_pcie *pcie;
198
199 struct fdt_resource regs;
200 unsigned int num_lanes;
201 unsigned int index;
202
203 struct list_head list;
204};
205
206struct tegra_pcie_soc {
207 unsigned int num_ports;
208 unsigned long pads_pll_ctl;
209 unsigned long tx_ref_sel;
210 unsigned long afi_pex2_ctrl;
211 u32 pads_refclk_cfg0;
212 u32 pads_refclk_cfg1;
213 bool has_pex_clkreq_en;
214 bool has_pex_bias_ctrl;
215 bool has_cml_clk;
216 bool has_gen2;
217 bool force_pca_enable;
218};
219
220struct tegra_pcie {
221 struct resource pads;
222 struct resource afi;
223 struct resource cs;
224
225 struct list_head ports;
226 unsigned long xbar;
227
228 const struct tegra_pcie_soc *soc;
229
230#ifdef CONFIG_TEGRA186
231 struct clk clk_afi;
232 struct clk clk_pex;
233 struct reset_ctl reset_afi;
234 struct reset_ctl reset_pex;
235 struct reset_ctl reset_pcie_x;
236 struct power_domain pwrdom;
237#else
238 struct tegra_xusb_phy *phy;
239#endif
240};
241
242static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
243 unsigned long offset)
244{
245 writel(value, pcie->afi.start + offset);
246}
247
248static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
249{
250 return readl(pcie->afi.start + offset);
251}
252
253static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
254 unsigned long offset)
255{
256 writel(value, pcie->pads.start + offset);
257}
258
259#ifndef CONFIG_TEGRA186
260static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
261{
262 return readl(pcie->pads.start + offset);
263}
264#endif
265
266static unsigned long rp_readl(struct tegra_pcie_port *port,
267 unsigned long offset)
268{
269 return readl(port->regs.start + offset);
270}
271
272static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
273 unsigned long offset)
274{
275 writel(value, port->regs.start + offset);
276}
277
278static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
279 int where, unsigned long *address)
280{
281 unsigned int bus = PCI_BUS(bdf);
282
283 if (bus == 0) {
284 unsigned int dev = PCI_DEV(bdf);
285 struct tegra_pcie_port *port;
286
287 list_for_each_entry(port, &pcie->ports, list) {
288 if (port->index + 1 == dev) {
289 *address = port->regs.start + (where & ~3);
290 return 0;
291 }
292 }
293 return -EFAULT;
294 } else {
295#ifdef CONFIG_TEGRA20
296 unsigned int dev = PCI_DEV(bdf);
297 if (dev != 0)
298 return -EFAULT;
299#endif
300
301 *address = pcie->cs.start +
302 (PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf),
303 PCI_FUNC(bdf), where) & ~PCI_CONF1_ENABLE);
304 return 0;
305 }
306}
307
308static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
309 uint offset, ulong *valuep,
310 enum pci_size_t size)
311{
312 struct tegra_pcie *pcie = dev_get_priv(bus);
313 unsigned long address, value;
314 int err;
315
316 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
317 if (err < 0) {
318 value = 0xffffffff;
319 goto done;
320 }
321
322 value = readl(address);
323
324#ifdef CONFIG_TEGRA20
325
326 if (PCI_BUS(bdf) == 0) {
327 if ((offset & ~3) == PCI_CLASS_REVISION) {
328 value &= ~0x00ff0000;
329 value |= PCI_CLASS_BRIDGE_PCI << 16;
330 }
331 }
332#endif
333
334done:
335 *valuep = pci_conv_32_to_size(value, offset, size);
336
337 return 0;
338}
339
340static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
341 uint offset, ulong value,
342 enum pci_size_t size)
343{
344 struct tegra_pcie *pcie = dev_get_priv(bus);
345 unsigned long address;
346 ulong old;
347 int err;
348
349 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
350 if (err < 0)
351 return 0;
352
353 old = readl(address);
354 value = pci_conv_size_to_32(old, value, offset, size);
355 writel(value, address);
356
357 return 0;
358}
359
360static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
361{
362 const u32 *addr;
363 int len;
364
365 addr = ofnode_get_property(node, "assigned-addresses", &len);
366 if (!addr) {
367 pr_err("property \"assigned-addresses\" not found");
368 return -FDT_ERR_NOTFOUND;
369 }
370
371 port->regs.start = fdt32_to_cpu(addr[2]);
372 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
373
374 return 0;
375}
376
377static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
378 enum tegra_pci_id id, unsigned long *xbar)
379{
380 switch (id) {
381 case TEGRA20_PCIE:
382 switch (lanes) {
383 case 0x00000004:
384 debug("single-mode configuration\n");
385 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
386 return 0;
387
388 case 0x00000202:
389 debug("dual-mode configuration\n");
390 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
391 return 0;
392 }
393 break;
394 case TEGRA30_PCIE:
395 switch (lanes) {
396 case 0x00000204:
397 debug("4x1, 2x1 configuration\n");
398 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
399 return 0;
400
401 case 0x00020202:
402 debug("2x3 configuration\n");
403 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
404 return 0;
405
406 case 0x00010104:
407 debug("4x1, 1x2 configuration\n");
408 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
409 return 0;
410 }
411 break;
412 case TEGRA124_PCIE:
413 case TEGRA210_PCIE:
414 switch (lanes) {
415 case 0x0000104:
416 debug("4x1, 1x1 configuration\n");
417 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
418 return 0;
419
420 case 0x0000102:
421 debug("2x1, 1x1 configuration\n");
422 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
423 return 0;
424 }
425 break;
426 case TEGRA186_PCIE:
427 switch (lanes) {
428 case 0x0010004:
429 debug("x4 x1 configuration\n");
430 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
431 return 0;
432
433 case 0x0010102:
434 debug("x2 x1 x1 configuration\n");
435 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
436 return 0;
437
438 case 0x0010101:
439 debug("x1 x1 x1 configuration\n");
440 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
441 return 0;
442 }
443 break;
444 default:
445 break;
446 }
447
448 return -FDT_ERR_NOTFOUND;
449}
450
451static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
452{
453 struct fdt_pci_addr addr;
454 int err;
455
456 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
457 if (err < 0) {
458 pr_err("failed to parse \"nvidia,num-lanes\" property");
459 return err;
460 }
461
462 *lanes = err;
463
464 err = ofnode_read_pci_addr(node, 0, "reg", &addr);
465 if (err < 0) {
466 pr_err("failed to parse \"reg\" property");
467 return err;
468 }
469
470 *index = PCI_DEV(addr.phys_hi) - 1;
471
472 return 0;
473}
474
475int __weak tegra_pcie_board_init(void)
476{
477 return 0;
478}
479
480static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
481 struct tegra_pcie *pcie)
482{
483 ofnode subnode;
484 u32 lanes = 0;
485 int err;
486
487 err = dev_read_resource(dev, 0, &pcie->pads);
488 if (err < 0) {
489 pr_err("resource \"pads\" not found");
490 return err;
491 }
492
493 err = dev_read_resource(dev, 1, &pcie->afi);
494 if (err < 0) {
495 pr_err("resource \"afi\" not found");
496 return err;
497 }
498
499 err = dev_read_resource(dev, 2, &pcie->cs);
500 if (err < 0) {
501 pr_err("resource \"cs\" not found");
502 return err;
503 }
504
505 err = tegra_pcie_board_init();
506 if (err < 0) {
507 pr_err("tegra_pcie_board_init() failed: err=%d", err);
508 return err;
509 }
510
511#ifndef CONFIG_TEGRA186
512 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
513 if (pcie->phy) {
514 err = tegra_xusb_phy_prepare(pcie->phy);
515 if (err < 0) {
516 pr_err("failed to prepare PHY: %d", err);
517 return err;
518 }
519 }
520#endif
521
522 dev_for_each_subnode(subnode, dev) {
523 unsigned int index = 0, num_lanes = 0;
524 struct tegra_pcie_port *port;
525
526 err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
527 if (err < 0) {
528 pr_err("failed to obtain root port info");
529 continue;
530 }
531
532 lanes |= num_lanes << (index << 3);
533
534 if (!ofnode_is_available(subnode))
535 continue;
536
537 port = malloc(sizeof(*port));
538 if (!port)
539 continue;
540
541 memset(port, 0, sizeof(*port));
542 port->num_lanes = num_lanes;
543 port->index = index;
544
545 err = tegra_pcie_port_parse_dt(subnode, port);
546 if (err < 0) {
547 free(port);
548 continue;
549 }
550
551 list_add_tail(&port->list, &pcie->ports);
552 port->pcie = pcie;
553 }
554
555 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
556 &pcie->xbar);
557 if (err < 0) {
558 pr_err("invalid lane configuration");
559 return err;
560 }
561
562 return 0;
563}
564
565#ifdef CONFIG_TEGRA186
566static int tegra_pcie_power_on(struct tegra_pcie *pcie)
567{
568 int ret;
569
570 ret = power_domain_on(&pcie->pwrdom);
571 if (ret) {
572 pr_err("power_domain_on() failed: %d\n", ret);
573 return ret;
574 }
575
576 ret = clk_enable(&pcie->clk_afi);
577 if (ret) {
578 pr_err("clk_enable(afi) failed: %d\n", ret);
579 return ret;
580 }
581
582 ret = clk_enable(&pcie->clk_pex);
583 if (ret) {
584 pr_err("clk_enable(pex) failed: %d\n", ret);
585 return ret;
586 }
587
588 ret = reset_deassert(&pcie->reset_afi);
589 if (ret) {
590 pr_err("reset_deassert(afi) failed: %d\n", ret);
591 return ret;
592 }
593
594 ret = reset_deassert(&pcie->reset_pex);
595 if (ret) {
596 pr_err("reset_deassert(pex) failed: %d\n", ret);
597 return ret;
598 }
599
600 return 0;
601}
602#else
603static int tegra_pcie_power_on(struct tegra_pcie *pcie)
604{
605 const struct tegra_pcie_soc *soc = pcie->soc;
606 unsigned long value;
607 int err;
608
609
610 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
611 reset_set_enable(PERIPH_ID_AFI, 1);
612 reset_set_enable(PERIPH_ID_PCIE, 1);
613
614 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
615 if (err < 0) {
616 pr_err("failed to power off PCIe partition: %d", err);
617 return err;
618 }
619
620 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
621 PERIPH_ID_PCIE);
622 if (err < 0) {
623 pr_err("failed to power up PCIe partition: %d", err);
624 return err;
625 }
626
627
628 reset_set_enable(PERIPH_ID_AFI, 0);
629
630
631 clock_enable(PERIPH_ID_AFI);
632
633 if (soc->has_cml_clk) {
634
635 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
636 value |= (1 << 0);
637 value &= ~(1 << 1);
638 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
639 }
640
641 err = tegra_plle_enable();
642 if (err < 0) {
643 pr_err("failed to enable PLLE: %d\n", err);
644 return err;
645 }
646
647 return 0;
648}
649
650static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
651{
652 const struct tegra_pcie_soc *soc = pcie->soc;
653 unsigned long start = get_timer(0);
654 u32 value;
655
656 while (get_timer(start) < timeout) {
657 value = pads_readl(pcie, soc->pads_pll_ctl);
658 if (value & PADS_PLL_CTL_LOCKDET)
659 return 0;
660 }
661
662 return -ETIMEDOUT;
663}
664
665static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
666{
667 const struct tegra_pcie_soc *soc = pcie->soc;
668 u32 value;
669 int err;
670
671
672 pads_writel(pcie, 0, PADS_CTL_SEL);
673
674
675 value = pads_readl(pcie, PADS_CTL);
676 value |= PADS_CTL_IDDQ_1L;
677 pads_writel(pcie, value, PADS_CTL);
678
679
680
681
682
683 value = pads_readl(pcie, soc->pads_pll_ctl);
684 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
685 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
686 pads_writel(pcie, value, soc->pads_pll_ctl);
687
688
689 value = pads_readl(pcie, soc->pads_pll_ctl);
690 value &= ~PADS_PLL_CTL_RST_B4SM;
691 pads_writel(pcie, value, soc->pads_pll_ctl);
692
693 udelay(20);
694
695
696 value = pads_readl(pcie, soc->pads_pll_ctl);
697 value |= PADS_PLL_CTL_RST_B4SM;
698 pads_writel(pcie, value, soc->pads_pll_ctl);
699
700
701 err = tegra_pcie_pll_wait(pcie, 500);
702 if (err < 0) {
703 pr_err("PLL failed to lock: %d", err);
704 return err;
705 }
706
707
708 value = pads_readl(pcie, PADS_CTL);
709 value &= ~PADS_CTL_IDDQ_1L;
710 pads_writel(pcie, value, PADS_CTL);
711
712
713 value = pads_readl(pcie, PADS_CTL);
714 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
715 pads_writel(pcie, value, PADS_CTL);
716
717 return 0;
718}
719#endif
720
721static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
722{
723 const struct tegra_pcie_soc *soc = pcie->soc;
724 struct tegra_pcie_port *port;
725 u32 value;
726 int err;
727
728#ifdef CONFIG_TEGRA186
729 {
730#else
731 if (pcie->phy) {
732#endif
733 value = afi_readl(pcie, AFI_PLLE_CONTROL);
734 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
735 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
736 afi_writel(pcie, value, AFI_PLLE_CONTROL);
737 }
738
739 if (soc->has_pex_bias_ctrl)
740 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
741
742 value = afi_readl(pcie, AFI_PCIE_CONFIG);
743 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
744 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
745
746 list_for_each_entry(port, &pcie->ports, list)
747 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
748
749 afi_writel(pcie, value, AFI_PCIE_CONFIG);
750
751 value = afi_readl(pcie, AFI_FUSE);
752
753 if (soc->has_gen2)
754 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
755 else
756 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
757
758 afi_writel(pcie, value, AFI_FUSE);
759
760#ifndef CONFIG_TEGRA186
761 if (pcie->phy)
762 err = tegra_xusb_phy_enable(pcie->phy);
763 else
764 err = tegra_pcie_phy_enable(pcie);
765
766 if (err < 0) {
767 pr_err("failed to power on PHY: %d\n", err);
768 return err;
769 }
770#endif
771
772
773#ifdef CONFIG_TEGRA186
774 err = reset_deassert(&pcie->reset_pcie_x);
775 if (err) {
776 pr_err("reset_deassert(pcie_x) failed: %d\n", err);
777 return err;
778 }
779#else
780 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
781#endif
782
783
784 value = afi_readl(pcie, AFI_CONFIGURATION);
785 value |= AFI_CONFIGURATION_EN_FPCI;
786 afi_writel(pcie, value, AFI_CONFIGURATION);
787
788
789 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
790 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
791 afi_writel(pcie, 0, AFI_INTR_MASK);
792 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
793
794 return 0;
795}
796
797static int tegra_pcie_setup_translations(struct udevice *bus)
798{
799 struct tegra_pcie *pcie = dev_get_priv(bus);
800 unsigned long fpci, axi, size;
801 struct pci_region *io, *mem, *pref;
802 int count;
803
804
805 fpci = 0xfe100000;
806 size = resource_size(&pcie->cs);
807 axi = pcie->cs.start;
808
809 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
810 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
811 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
812
813 count = pci_get_regions(bus, &io, &mem, &pref);
814 if (count != 3)
815 return -EINVAL;
816
817
818 fpci = 0xfdfc0000;
819 size = io->size;
820 axi = io->phys_start;
821
822 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
823 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
824 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
825
826
827 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
828 size = pref->size;
829 axi = pref->phys_start;
830
831 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
832 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
833 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
834
835
836 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
837 size = mem->size;
838 axi = mem->phys_start;
839
840 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
841 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
842 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
843
844
845 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
846 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
847 afi_writel(pcie, 0, AFI_FPCI_BAR4);
848
849 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
850 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
851 afi_writel(pcie, 0, AFI_FPCI_BAR5);
852
853
854 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
855 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
856 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
857 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
858
859
860 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
861 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
862 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
863 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
864
865 return 0;
866}
867
868static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
869{
870 unsigned long ret = 0;
871
872 switch (port->index) {
873 case 0:
874 ret = AFI_PEX0_CTRL;
875 break;
876
877 case 1:
878 ret = AFI_PEX1_CTRL;
879 break;
880
881 case 2:
882 ret = port->pcie->soc->afi_pex2_ctrl;
883 break;
884 }
885
886 return ret;
887}
888
889void tegra_pcie_port_reset(struct tegra_pcie_port *port)
890{
891 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
892 unsigned long value;
893
894
895 value = afi_readl(port->pcie, ctrl);
896 value &= ~AFI_PEX_CTRL_RST;
897 afi_writel(port->pcie, value, ctrl);
898
899 udelay(2000);
900
901 value = afi_readl(port->pcie, ctrl);
902 value |= AFI_PEX_CTRL_RST;
903 afi_writel(port->pcie, value, ctrl);
904}
905
906int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port)
907{
908 return port->index;
909}
910
911void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
912{
913 tegra_pcie_port_reset(port);
914}
915
916static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
917{
918 struct tegra_pcie *pcie = port->pcie;
919 const struct tegra_pcie_soc *soc = pcie->soc;
920 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
921 unsigned long value;
922
923
924 value = afi_readl(pcie, ctrl);
925 value |= AFI_PEX_CTRL_REFCLK_EN;
926
927 if (pcie->soc->has_pex_clkreq_en)
928 value |= AFI_PEX_CTRL_CLKREQ_EN;
929
930 value |= AFI_PEX_CTRL_OVERRIDE_EN;
931
932 afi_writel(pcie, value, ctrl);
933
934 tegra_pcie_board_port_reset(port);
935
936 if (soc->force_pca_enable) {
937 value = rp_readl(port, RP_VEND_CTL2);
938 value |= RP_VEND_CTL2_PCA_ENABLE;
939 rp_writel(port, value, RP_VEND_CTL2);
940 }
941
942
943 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
944 if (soc->num_ports > 2)
945 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
946}
947
948static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
949{
950 unsigned int retries = 3;
951 unsigned long value;
952
953 value = rp_readl(port, RP_PRIV_MISC);
954 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
955 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
956 rp_writel(port, value, RP_PRIV_MISC);
957
958 do {
959 unsigned int timeout = 200;
960
961 do {
962 value = rp_readl(port, RP_VEND_XP);
963 if (value & RP_VEND_XP_DL_UP)
964 break;
965
966 udelay(2000);
967 } while (--timeout);
968
969 if (!timeout) {
970 debug("link %u down, retrying\n", port->index);
971 goto retry;
972 }
973
974 timeout = 200;
975
976 do {
977 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
978 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
979 return true;
980
981 udelay(2000);
982 } while (--timeout);
983
984retry:
985 tegra_pcie_board_port_reset(port);
986 } while (--retries);
987
988 return false;
989}
990
991static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
992{
993 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
994 unsigned long value;
995
996
997 value = afi_readl(port->pcie, ctrl);
998 value &= ~AFI_PEX_CTRL_RST;
999 afi_writel(port->pcie, value, ctrl);
1000
1001
1002 value = afi_readl(port->pcie, ctrl);
1003 value &= ~AFI_PEX_CTRL_REFCLK_EN;
1004 afi_writel(port->pcie, value, ctrl);
1005}
1006
1007static void tegra_pcie_port_free(struct tegra_pcie_port *port)
1008{
1009 list_del(&port->list);
1010 free(port);
1011}
1012
1013static int tegra_pcie_enable(struct tegra_pcie *pcie)
1014{
1015 struct tegra_pcie_port *port, *tmp;
1016
1017 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1018 debug("probing port %u, using %u lanes\n", port->index,
1019 port->num_lanes);
1020
1021 tegra_pcie_port_enable(port);
1022
1023 if (tegra_pcie_port_check_link(port))
1024 continue;
1025
1026 debug("link %u down, ignoring\n", port->index);
1027
1028 tegra_pcie_port_disable(port);
1029 tegra_pcie_port_free(port);
1030 }
1031
1032 return 0;
1033}
1034
1035static const struct tegra_pcie_soc pci_tegra_soc[] = {
1036 [TEGRA20_PCIE] = {
1037 .num_ports = 2,
1038 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1039 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1040 .pads_refclk_cfg0 = 0xfa5cfa5c,
1041 .has_pex_clkreq_en = false,
1042 .has_pex_bias_ctrl = false,
1043 .has_cml_clk = false,
1044 .has_gen2 = false,
1045 },
1046 [TEGRA30_PCIE] = {
1047 .num_ports = 3,
1048 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1049 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1050 .afi_pex2_ctrl = AFI_PEX2_CTRL,
1051 .pads_refclk_cfg0 = 0xfa5cfa5c,
1052 .pads_refclk_cfg1 = 0xfa5cfa5c,
1053 .has_pex_clkreq_en = true,
1054 .has_pex_bias_ctrl = true,
1055 .has_cml_clk = true,
1056 .has_gen2 = false,
1057 },
1058 [TEGRA124_PCIE] = {
1059 .num_ports = 2,
1060 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1061 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1062 .pads_refclk_cfg0 = 0x44ac44ac,
1063 .has_pex_clkreq_en = true,
1064 .has_pex_bias_ctrl = true,
1065 .has_cml_clk = true,
1066 .has_gen2 = true,
1067 },
1068 [TEGRA210_PCIE] = {
1069 .num_ports = 2,
1070 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1071 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1072 .pads_refclk_cfg0 = 0x90b890b8,
1073 .has_pex_clkreq_en = true,
1074 .has_pex_bias_ctrl = true,
1075 .has_cml_clk = true,
1076 .has_gen2 = true,
1077 .force_pca_enable = true,
1078 },
1079 [TEGRA186_PCIE] = {
1080 .num_ports = 3,
1081 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
1082 .pads_refclk_cfg0 = 0x80b880b8,
1083 .pads_refclk_cfg1 = 0x000480b8,
1084 .has_pex_clkreq_en = true,
1085 .has_pex_bias_ctrl = true,
1086 .has_gen2 = true,
1087 },
1088};
1089
1090static int pci_tegra_of_to_plat(struct udevice *dev)
1091{
1092 struct tegra_pcie *pcie = dev_get_priv(dev);
1093 enum tegra_pci_id id;
1094
1095 id = dev_get_driver_data(dev);
1096 pcie->soc = &pci_tegra_soc[id];
1097
1098 INIT_LIST_HEAD(&pcie->ports);
1099
1100 if (tegra_pcie_parse_dt(dev, id, pcie))
1101 return -EINVAL;
1102
1103 return 0;
1104}
1105
1106static int pci_tegra_probe(struct udevice *dev)
1107{
1108 struct tegra_pcie *pcie = dev_get_priv(dev);
1109 int err;
1110
1111#ifdef CONFIG_TEGRA186
1112 err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1113 if (err) {
1114 debug("clk_get_by_name(afi) failed: %d\n", err);
1115 return err;
1116 }
1117
1118 err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1119 if (err) {
1120 debug("clk_get_by_name(pex) failed: %d\n", err);
1121 return err;
1122 }
1123
1124 err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1125 if (err) {
1126 debug("reset_get_by_name(afi) failed: %d\n", err);
1127 return err;
1128 }
1129
1130 err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1131 if (err) {
1132 debug("reset_get_by_name(pex) failed: %d\n", err);
1133 return err;
1134 }
1135
1136 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1137 if (err) {
1138 debug("reset_get_by_name(pcie_x) failed: %d\n", err);
1139 return err;
1140 }
1141
1142 err = power_domain_get(dev, &pcie->pwrdom);
1143 if (err) {
1144 debug("power_domain_get() failed: %d\n", err);
1145 return err;
1146 }
1147#endif
1148
1149 err = tegra_pcie_power_on(pcie);
1150 if (err < 0) {
1151 pr_err("failed to power on");
1152 return err;
1153 }
1154
1155 err = tegra_pcie_enable_controller(pcie);
1156 if (err < 0) {
1157 pr_err("failed to enable controller");
1158 return err;
1159 }
1160
1161 err = tegra_pcie_setup_translations(dev);
1162 if (err < 0) {
1163 pr_err("failed to decode ranges");
1164 return err;
1165 }
1166
1167 err = tegra_pcie_enable(pcie);
1168 if (err < 0) {
1169 pr_err("failed to enable PCIe");
1170 return err;
1171 }
1172
1173 return 0;
1174}
1175
1176static const struct dm_pci_ops pci_tegra_ops = {
1177 .read_config = pci_tegra_read_config,
1178 .write_config = pci_tegra_write_config,
1179};
1180
1181static const struct udevice_id pci_tegra_ids[] = {
1182 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1183 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1184 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1185 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1186 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
1187 { }
1188};
1189
1190U_BOOT_DRIVER(pci_tegra) = {
1191 .name = "pci_tegra",
1192 .id = UCLASS_PCI,
1193 .of_match = pci_tegra_ids,
1194 .ops = &pci_tegra_ops,
1195 .of_to_plat = pci_tegra_of_to_plat,
1196 .probe = pci_tegra_probe,
1197 .priv_auto = sizeof(struct tegra_pcie),
1198};
1199
