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8#include <common.h>
9#include <dm.h>
10#include <pci.h>
11#include <asm/global_data.h>
12#include <linux/bitops.h>
13
14#include <asm/io.h>
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20struct xilinx_pcie {
21 void *cfg_base;
22};
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25#define XILINX_PCIE_REG_PSCR 0x144
26#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
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36static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
37{
38 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
39
40 return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
41}
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59static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
60 uint offset, void **paddress)
61{
62 struct xilinx_pcie *pcie = dev_get_priv(udev);
63 unsigned int bus = PCI_BUS(bdf);
64 unsigned int dev = PCI_DEV(bdf);
65 unsigned int func = PCI_FUNC(bdf);
66 void *addr;
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68 if ((bus > 0) && !pcie_xilinx_link_up(pcie))
69 return -ENODEV;
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75 if ((bus < 2) && (dev > 0))
76 return -ENODEV;
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78 addr = pcie->cfg_base;
79 addr += PCIE_ECAM_OFFSET(bus, dev, func, offset);
80 *paddress = addr;
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82 return 0;
83}
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99static int pcie_xilinx_read_config(const struct udevice *bus, pci_dev_t bdf,
100 uint offset, ulong *valuep,
101 enum pci_size_t size)
102{
103 return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
104 bdf, offset, valuep, size);
105}
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121static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
122 uint offset, ulong value,
123 enum pci_size_t size)
124{
125 return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
126 bdf, offset, value, size);
127}
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139static int pcie_xilinx_of_to_plat(struct udevice *dev)
140{
141 struct xilinx_pcie *pcie = dev_get_priv(dev);
142 struct fdt_resource reg_res;
143 DECLARE_GLOBAL_DATA_PTR;
144 int err;
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146 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
147 0, ®_res);
148 if (err < 0) {
149 pr_err("\"reg\" resource not found\n");
150 return err;
151 }
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153 pcie->cfg_base = map_physmem(reg_res.start,
154 fdt_resource_size(®_res),
155 MAP_NOCACHE);
156
157 return 0;
158}
159
160static const struct dm_pci_ops pcie_xilinx_ops = {
161 .read_config = pcie_xilinx_read_config,
162 .write_config = pcie_xilinx_write_config,
163};
164
165static const struct udevice_id pcie_xilinx_ids[] = {
166 { .compatible = "xlnx,axi-pcie-host-1.00.a" },
167 { }
168};
169
170U_BOOT_DRIVER(pcie_xilinx) = {
171 .name = "pcie_xilinx",
172 .id = UCLASS_PCI,
173 .of_match = pcie_xilinx_ids,
174 .ops = &pcie_xilinx_ops,
175 .of_to_plat = pcie_xilinx_of_to_plat,
176 .priv_auto = sizeof(struct xilinx_pcie),
177};
178