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6#ifndef _RAM_STM32MP1_DDR_REGS_H
7#define _RAM_STM32MP1_DDR_REGS_H
8
9#include <linux/bitops.h>
10
11
12struct stm32mp1_ddrctl {
13 u32 mstr ;
14 u32 stat;
15 u8 reserved008[0x10 - 0x8];
16 u32 mrctrl0;
17 u32 mrctrl1;
18 u32 mrstat;
19 u32 reserved01c;
20 u32 derateen;
21 u32 derateint;
22 u8 reserved028[0x30 - 0x28];
23 u32 pwrctl;
24 u32 pwrtmg;
25 u32 hwlpctl;
26 u8 reserved03c[0x50 - 0x3C];
27 u32 rfshctl0;
28 u32 reserved054;
29 u32 reserved058;
30 u32 reserved05C;
31 u32 rfshctl3;
32 u32 rfshtmg;
33 u8 reserved068[0xc0 - 0x68];
34 u32 crcparctl0;
35 u32 reserved0c4;
36 u32 reserved0c8;
37 u32 crcparstat;
38 u32 init0;
39 u32 init1;
40 u32 init2;
41 u32 init3;
42 u32 init4;
43 u32 init5;
44 u32 reserved0e8;
45 u32 reserved0ec;
46 u32 dimmctl;
47 u8 reserved0f4[0x100 - 0xf4];
48 u32 dramtmg0;
49 u32 dramtmg1;
50 u32 dramtmg2;
51 u32 dramtmg3;
52 u32 dramtmg4;
53 u32 dramtmg5;
54 u32 dramtmg6;
55 u32 dramtmg7;
56 u32 dramtmg8;
57 u8 reserved124[0x138 - 0x124];
58 u32 dramtmg14;
59 u32 dramtmg15;
60 u8 reserved140[0x180 - 0x140];
61 u32 zqctl0;
62 u32 zqctl1;
63 u32 zqctl2;
64 u32 zqstat;
65 u32 dfitmg0;
66 u32 dfitmg1;
67 u32 dfilpcfg0;
68 u32 reserved19c;
69 u32 dfiupd0;
70 u32 dfiupd1;
71 u32 dfiupd2;
72 u32 reserved1ac;
73 u32 dfimisc;
74 u8 reserved1b4[0x1bc - 0x1b4];
75 u32 dfistat;
76 u8 reserved1c0[0x1c4 - 0x1c0];
77 u32 dfiphymstr;
78 u8 reserved1c8[0x204 - 0x1c8];
79 u32 addrmap1;
80 u32 addrmap2;
81 u32 addrmap3;
82 u32 addrmap4;
83 u32 addrmap5;
84 u32 addrmap6;
85 u8 reserved21c[0x224 - 0x21c];
86 u32 addrmap9;
87 u32 addrmap10;
88 u32 addrmap11;
89 u8 reserved230[0x240 - 0x230];
90 u32 odtcfg;
91 u32 odtmap;
92 u8 reserved248[0x250 - 0x248];
93 u32 sched;
94 u32 sched1;
95 u32 reserved258;
96 u32 perfhpr1;
97 u32 reserved260;
98 u32 perflpr1;
99 u32 reserved268;
100 u32 perfwr1;
101 u8 reserved27c[0x300 - 0x270];
102 u32 dbg0;
103 u32 dbg1;
104 u32 dbgcam;
105 u32 dbgcmd;
106 u32 dbgstat;
107 u8 reserved314[0x320 - 0x314];
108 u32 swctl;
109 u32 swstat;
110 u8 reserved328[0x36c - 0x328];
111 u32 poisoncfg;
112 u32 poisonstat;
113 u8 reserved374[0x3fc - 0x374];
114
115
116 u32 pstat;
117 u32 pccfg;
118
119
120 u32 pcfgr_0;
121 u32 pcfgw_0;
122 u8 reserved40c[0x490 - 0x40c];
123 u32 pctrl_0;
124 u32 pcfgqos0_0;
125 u32 pcfgqos1_0;
126 u32 pcfgwqos0_0;
127 u32 pcfgwqos1_0;
128 u8 reserved4a4[0x4b4 - 0x4a4];
129
130
131 u32 pcfgr_1;
132 u32 pcfgw_1;
133 u8 reserved4bc[0x540 - 0x4bc];
134 u32 pctrl_1;
135 u32 pcfgqos0_1;
136 u32 pcfgqos1_1;
137 u32 pcfgwqos0_1;
138 u32 pcfgwqos1_1;
139};
140
141
142struct stm32mp1_ddrphy {
143 u32 ridr;
144 u32 pir;
145 u32 pgcr;
146 u32 pgsr;
147 u32 dllgcr;
148 u32 acdllcr;
149 u32 ptr0;
150 u32 ptr1;
151 u32 ptr2;
152 u32 aciocr;
153 u32 dxccr;
154 u32 dsgcr;
155 u32 dcr;
156 u32 dtpr0;
157 u32 dtpr1;
158 u32 dtpr2;
159 u32 mr0;
160 u32 mr1;
161 u32 mr2;
162 u32 mr3;
163 u32 odtcr;
164 u32 dtar;
165 u32 dtdr0;
166 u32 dtdr1;
167 u8 res1[0x0c0 - 0x060];
168 u32 dcuar;
169 u32 dcudr;
170 u32 dcurr;
171 u32 dculr;
172 u32 dcugcr;
173 u32 dcutpr;
174 u32 dcusr0;
175 u32 dcusr1;
176 u8 res2[0x100 - 0xe0];
177 u32 bistrr;
178 u32 bistmskr0;
179 u32 bistmskr1;
180 u32 bistwcr;
181 u32 bistlsr;
182 u32 bistar0;
183 u32 bistar1;
184 u32 bistar2;
185 u32 bistupdr;
186 u32 bistgsr;
187 u32 bistwer;
188 u32 bistber0;
189 u32 bistber1;
190 u32 bistber2;
191 u32 bistwcsr;
192 u32 bistfwr0;
193 u32 bistfwr1;
194 u8 res3[0x178 - 0x144];
195 u32 gpr0;
196 u32 gpr1;
197 u32 zq0cr0;
198 u32 zq0cr1;
199 u32 zq0sr0;
200 u32 zq0sr1;
201 u8 res4[0x1C0 - 0x190];
202 u32 dx0gcr;
203 u32 dx0gsr0;
204 u32 dx0gsr1;
205 u32 dx0dllcr;
206 u32 dx0dqtr;
207 u32 dx0dqstr;
208 u8 res5[0x200 - 0x1d8];
209 u32 dx1gcr;
210 u32 dx1gsr0;
211 u32 dx1gsr1;
212 u32 dx1dllcr;
213 u32 dx1dqtr;
214 u32 dx1dqstr;
215 u8 res6[0x240 - 0x218];
216 u32 dx2gcr;
217 u32 dx2gsr0;
218 u32 dx2gsr1;
219 u32 dx2dllcr;
220 u32 dx2dqtr;
221 u32 dx2dqstr;
222 u8 res7[0x280 - 0x258];
223 u32 dx3gcr;
224 u32 dx3gsr0;
225 u32 dx3gsr1;
226 u32 dx3dllcr;
227 u32 dx3dqtr;
228 u32 dx3dqstr;
229};
230
231#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40))
232#define DXNGCR(phy, byte) DXN(phy, 0x1c0, byte)
233#define DXNDLLCR(phy, byte) DXN(phy, 0x1cc, byte)
234#define DXNDQTR(phy, byte) DXN(phy, 0x1d0, byte)
235#define DXNDQSTR(phy, byte) DXN(phy, 0x1d4, byte)
236
237
238#define DDRCTRL_MSTR_DDR3 BIT(0)
239#define DDRCTRL_MSTR_LPDDR2 BIT(2)
240#define DDRCTRL_MSTR_LPDDR3 BIT(3)
241#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
242#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT 12
243#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
244#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)
245#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12)
246#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
247
248#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
249#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 1
250#define DDRCTRL_STAT_OPERATING_MODE_SR 3
251#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
252#define DDRCTRL_STAT_SELFREF_TYPE_ASR (3 << 4)
253#define DDRCTRL_STAT_SELFREF_TYPE_SR (2 << 4)
254
255#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE 0
256
257#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
258#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
259 (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
260#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
261#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
262#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
263
264#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
265
266#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0)
267#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
268#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3)
269#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
270
271#define DDRCTRL_PWRTMG_SELFREF_TO_X32(n) (((n) & 0xff) << 16)
272#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32(n) ((n) & 0x1f)
273
274#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0)
275
276#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
277
278#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
279#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
280
281#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000)
282#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL (BIT(30))
283
284#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
285
286#define DDRCTRL_SWCTL_SW_DONE BIT(0)
287
288#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
289
290#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
291
292
293#define DDRPHYC_PIR_INIT BIT(0)
294#define DDRPHYC_PIR_DLLSRST BIT(1)
295#define DDRPHYC_PIR_DLLLOCK BIT(2)
296#define DDRPHYC_PIR_ZCAL BIT(3)
297#define DDRPHYC_PIR_ITMSRST BIT(4)
298#define DDRPHYC_PIR_DRAMRST BIT(5)
299#define DDRPHYC_PIR_DRAMINIT BIT(6)
300#define DDRPHYC_PIR_QSTRN BIT(7)
301#define DDRPHYC_PIR_RVTRN BIT(8)
302#define DDRPHYC_PIR_ICPC BIT(16)
303#define DDRPHYC_PIR_ZCALBYP BIT(30)
304
305#define DDRPHYC_PGSR_IDONE BIT(0)
306#define DDRPHYC_PGSR_DTERR BIT(5)
307#define DDRPHYC_PGSR_DTIERR BIT(6)
308#define DDRPHYC_PGSR_DFTERR BIT(7)
309#define DDRPHYC_PGSR_RVERR BIT(8)
310#define DDRPHYC_PGSR_RVEIRR BIT(9)
311
312
313#define PWR_CR3 0x00C
314#define PWR_CR3_DDRSRDIS BIT(11)
315#define PWR_CR3_DDRRETEN BIT(12)
316
317#endif
318