LXR uboot/drivers/spi/pic32

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Microchip PIC32 SPI controller driver.
   4 *
   5 * Copyright (c) 2015, Microchip Technology Inc.
   6 *      Purna Chandra Mandal <purna.mandal@microchip.com>
   7 */
   8
   9#include <common.h>
  10#include <clk.h>
  11#include <dm.h>
  12#include <log.h>
  13#include <asm/global_data.h>
  14#include <linux/bitops.h>
  15#include <linux/compat.h>
  16#include <malloc.h>
  17#include <spi.h>
  18
  19#include <asm/types.h>
  20#include <asm/io.h>
  21#include <asm/gpio.h>
  22#include <dt-bindings/clock/microchip,clock.h>
  23#include <mach/pic32.h>
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27/* PIC32 SPI controller registers */
  28struct pic32_reg_spi {
  29        struct pic32_reg_atomic ctrl;
  30        struct pic32_reg_atomic status;
  31        struct pic32_reg_atomic buf;
  32        struct pic32_reg_atomic baud;
  33        struct pic32_reg_atomic ctrl2;
  34};
  35
  36/* Bit fields in SPI Control Register */
  37#define PIC32_SPI_CTRL_MSTEN    BIT(5) /* Enable SPI Master */
  38#define PIC32_SPI_CTRL_CKP      BIT(6) /* active low */
  39#define PIC32_SPI_CTRL_CKE      BIT(8) /* Tx on falling edge */
  40#define PIC32_SPI_CTRL_SMP      BIT(9) /* Rx at middle or end of tx */
  41#define PIC32_SPI_CTRL_BPW_MASK 0x03   /* Bits per word */
  42#define  PIC32_SPI_CTRL_BPW_8           0x0
  43#define  PIC32_SPI_CTRL_BPW_16          0x1
  44#define  PIC32_SPI_CTRL_BPW_32          0x2
  45#define PIC32_SPI_CTRL_BPW_SHIFT        10
  46#define PIC32_SPI_CTRL_ON       BIT(15) /* Macro enable */
  47#define PIC32_SPI_CTRL_ENHBUF   BIT(16) /* Enable enhanced buffering */
  48#define PIC32_SPI_CTRL_MCLKSEL  BIT(23) /* Select SPI Clock src */
  49#define PIC32_SPI_CTRL_MSSEN    BIT(28) /* SPI macro will drive SS */
  50#define PIC32_SPI_CTRL_FRMEN    BIT(31) /* Enable framing mode */
  51
  52/* Bit fields in SPI Status Register */
  53#define PIC32_SPI_STAT_RX_OV            BIT(6) /* err, s/w needs to clear */
  54#define PIC32_SPI_STAT_TF_LVL_MASK      0x1f
  55#define PIC32_SPI_STAT_TF_LVL_SHIFT     16
  56#define PIC32_SPI_STAT_RF_LVL_MASK      0x1f
  57#define PIC32_SPI_STAT_RF_LVL_SHIFT     24
  58
  59/* Bit fields in SPI Baud Register */
  60#define PIC32_SPI_BAUD_MASK     0x1ff
  61
  62struct pic32_spi_priv {
  63        struct pic32_reg_spi    *regs;
  64        u32                     fifo_depth; /* FIFO depth in bytes */
  65        u32                     fifo_n_word; /* FIFO depth in words */
  66        struct gpio_desc        cs_gpio;
  67
  68        /* Current SPI slave specific */
  69        ulong                   clk_rate;
  70        u32                     speed_hz; /* spi-clk rate */
  71        int                     mode;
  72
  73        /* Current message/transfer state */
  74        const void              *tx;
  75        const void              *tx_end;
  76        const void              *rx;
  77        const void              *rx_end;
  78        u32                     len;
  79
  80        /* SPI FiFo accessor */
  81        void (*rx_fifo)(struct pic32_spi_priv *);
  82        void (*tx_fifo)(struct pic32_spi_priv *);
  83};
  84
  85static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
  86{
  87        writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
  88}
  89
  90static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
  91{
  92        writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
  93}
  94
  95static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
  96{
  97        u32 sr = readl(&priv->regs->status.raw);
  98
  99        return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
 100}
 101
 102static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
 103{
 104        u32 sr = readl(&priv->regs->status.raw);
 105
 106        return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
 107}
 108
 109/* Return the max entries we can fill into tx fifo */
 110static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
 111{
 112        u32 tx_left, tx_room, rxtx_gap;
 113
 114        tx_left = (priv->tx_end - priv->tx) / n_bytes;
 115        tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
 116
 117        rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
 118        rxtx_gap /= n_bytes;
 119        return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
 120}
 121
 122/* Return the max entries we should read out of rx fifo */
 123static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
 124{
 125        u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
 126
 127        return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
 128}
 129
 130#define BUILD_SPI_FIFO_RW(__name, __type, __bwl)                \
 131static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv)  \
 132{                                                               \
 133        __type val;                                             \
 134        u32 mx = pic32_rx_max(priv, sizeof(__type));            \
 135                                                                \
 136        for (; mx; mx--) {                                      \
 137                val = read##__bwl(&priv->regs->buf.raw);        \
 138                if (priv->rx_end - priv->len)                   \
 139                        *(__type *)(priv->rx) = val;            \
 140                priv->rx += sizeof(__type);                     \
 141        }                                                       \
 142}                                                               \
 143                                                                \
 144static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv)  \
 145{                                                               \
 146        __type val;                                             \
 147        u32 mx = pic32_tx_max(priv, sizeof(__type));            \
 148                                                                \
 149        for (; mx ; mx--) {                                     \
 150                val = (__type) ~0U;                             \
 151                if (priv->tx_end - priv->len)                   \
 152                        val =  *(__type *)(priv->tx);           \
 153                write##__bwl(val, &priv->regs->buf.raw);        \
 154                priv->tx += sizeof(__type);                     \
 155        }                                                       \
 156}
 157BUILD_SPI_FIFO_RW(byte, u8, b);
 158BUILD_SPI_FIFO_RW(word, u16, w);
 159BUILD_SPI_FIFO_RW(dword, u32, l);
 160
 161static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
 162                                   unsigned int wordlen)
 163{
 164        u32 bits_per_word;
 165        u32 val;
 166
 167        switch (wordlen) {
 168        case 8:
 169                priv->rx_fifo = pic32_spi_rx_byte;
 170                priv->tx_fifo = pic32_spi_tx_byte;
 171                bits_per_word = PIC32_SPI_CTRL_BPW_8;
 172                break;
 173        case 16:
 174                priv->rx_fifo = pic32_spi_rx_word;
 175                priv->tx_fifo = pic32_spi_tx_word;
 176                bits_per_word = PIC32_SPI_CTRL_BPW_16;
 177                break;
 178        case 32:
 179                priv->rx_fifo = pic32_spi_rx_dword;
 180                priv->tx_fifo = pic32_spi_tx_dword;
 181                bits_per_word = PIC32_SPI_CTRL_BPW_32;
 182                break;
 183        default:
 184                printf("pic32-spi: unsupported wordlen\n");
 185                return -EINVAL;
 186        }
 187
 188        /* set bits-per-word */
 189        val = readl(&priv->regs->ctrl.raw);
 190        val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
 191        val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
 192        writel(val, &priv->regs->ctrl.raw);
 193
 194        /* calculate maximum number of words fifo can hold */
 195        priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
 196
 197        return 0;
 198}
 199
 200static int pic32_spi_claim_bus(struct udevice *slave)
 201{
 202        struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
 203
 204        /* enable chip */
 205        pic32_spi_enable(priv);
 206
 207        return 0;
 208}
 209
 210static int pic32_spi_release_bus(struct udevice *slave)
 211{
 212        struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
 213
 214        /* disable chip */
 215        pic32_spi_disable(priv);
 216
 217        return 0;
 218}
 219
 220static void spi_cs_activate(struct pic32_spi_priv *priv)
 221{
 222        if (!dm_gpio_is_valid(&priv->cs_gpio))
 223                return;
 224
 225        dm_gpio_set_value(&priv->cs_gpio, 1);
 226}
 227
 228static void spi_cs_deactivate(struct pic32_spi_priv *priv)
 229{
 230        if (!dm_gpio_is_valid(&priv->cs_gpio))
 231                return;
 232
 233        dm_gpio_set_value(&priv->cs_gpio, 0);
 234}
 235
 236static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
 237                          const void *tx_buf, void *rx_buf,
 238                          unsigned long flags)
 239{
 240        struct dm_spi_slave_plat *slave_plat;
 241        struct udevice *bus = slave->parent;
 242        struct pic32_spi_priv *priv;
 243        int len = bitlen / 8;
 244        int ret = 0;
 245        ulong tbase;
 246
 247        priv = dev_get_priv(bus);
 248        slave_plat = dev_get_parent_plat(slave);
 249
 250        debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
 251              dev_seq(bus), slave_plat->cs, flags);
 252        debug("msg tx %p, rx %p submitted of %d byte(s)\n",
 253              tx_buf, rx_buf, len);
 254
 255        /* assert cs */
 256        if (flags & SPI_XFER_BEGIN)
 257                spi_cs_activate(priv);
 258
 259        /* set current transfer information */
 260        priv->tx = tx_buf;
 261        priv->rx = rx_buf;
 262        priv->tx_end = priv->tx + len;
 263        priv->rx_end = priv->rx + len;
 264        priv->len = len;
 265
 266        /* transact by polling */
 267        tbase = get_timer(0);
 268        for (;;) {
 269                priv->tx_fifo(priv);
 270                priv->rx_fifo(priv);
 271
 272                /* received sufficient data */
 273                if (priv->rx >= priv->rx_end) {
 274                        ret = 0;
 275                        break;
 276                }
 277
 278                if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
 279                        printf("pic32_spi: error, xfer timedout.\n");
 280                        flags |= SPI_XFER_END;
 281                        ret = -ETIMEDOUT;
 282                        break;
 283                }
 284        }
 285
 286        /* deassert cs */
 287        if (flags & SPI_XFER_END)
 288                spi_cs_deactivate(priv);
 289
 290        return ret;
 291}
 292
 293static int pic32_spi_set_speed(struct udevice *bus, uint speed)
 294{
 295        struct pic32_spi_priv *priv = dev_get_priv(bus);
 296        u32 div;
 297
 298        debug("%s: %s, speed %u\n", __func__, bus->name, speed);
 299
 300        /* div = [clk_in / (2 * spi_clk)] - 1 */
 301        div = (priv->clk_rate / 2 / speed) - 1;
 302        div &= PIC32_SPI_BAUD_MASK;
 303        writel(div, &priv->regs->baud.raw);
 304
 305        priv->speed_hz = speed;
 306
 307        return 0;
 308}
 309
 310static int pic32_spi_set_mode(struct udevice *bus, uint mode)
 311{
 312        struct pic32_spi_priv *priv = dev_get_priv(bus);
 313        u32 val;
 314
 315        debug("%s: %s, mode %d\n", __func__, bus->name, mode);
 316
 317        /* set spi-clk mode */
 318        val = readl(&priv->regs->ctrl.raw);
 319        /* HIGH when idle */
 320        if (mode & SPI_CPOL)
 321                val |= PIC32_SPI_CTRL_CKP;
 322        else
 323                val &= ~PIC32_SPI_CTRL_CKP;
 324
 325        /* TX at idle-to-active clk transition */
 326        if (mode & SPI_CPHA)
 327                val &= ~PIC32_SPI_CTRL_CKE;
 328        else
 329                val |= PIC32_SPI_CTRL_CKE;
 330
 331        /* RX at end of tx */
 332        val |= PIC32_SPI_CTRL_SMP;
 333        writel(val, &priv->regs->ctrl.raw);
 334
 335        priv->mode = mode;
 336
 337        return 0;
 338}
 339
 340static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
 341{
 342        struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
 343
 344        return pic32_spi_set_word_size(priv, wordlen);
 345}
 346
 347static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
 348{
 349        u32 val;
 350
 351        /* disable module */
 352        pic32_spi_disable(priv);
 353
 354        val = readl(&priv->regs->ctrl);
 355
 356        /* enable enhanced fifo of 128bit deep */
 357        val |= PIC32_SPI_CTRL_ENHBUF;
 358        priv->fifo_depth = 16;
 359
 360        /* disable framing mode */
 361        val &= ~PIC32_SPI_CTRL_FRMEN;
 362
 363        /* enable master mode */
 364        val |= PIC32_SPI_CTRL_MSTEN;
 365
 366        /* select clk source */
 367        val &= ~PIC32_SPI_CTRL_MCLKSEL;
 368
 369        /* set manual /CS mode */
 370        val &= ~PIC32_SPI_CTRL_MSSEN;
 371
 372        writel(val, &priv->regs->ctrl);
 373
 374        /* clear rx overflow indicator */
 375        writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
 376}
 377
 378static int pic32_spi_probe(struct udevice *bus)
 379{
 380        struct pic32_spi_priv *priv = dev_get_priv(bus);
 381        struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
 382        int node = dev_of_offset(bus);
 383        struct udevice *clkdev;
 384        fdt_addr_t addr;
 385        fdt_size_t size;
 386        int ret;
 387
 388        debug("%s: %d, bus: %i\n", __func__, __LINE__, dev_seq(bus));
 389        addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
 390        if (addr == FDT_ADDR_T_NONE)
 391                return -EINVAL;
 392
 393        priv->regs = ioremap(addr, size);
 394        if (!priv->regs)
 395                return -EINVAL;
 396
 397        dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
 398                                        250000000);
 399        /* get clock rate */
 400        ret = clk_get_by_index(bus, 0, &clkdev);
 401        if (ret < 0) {
 402                printf("pic32-spi: error, clk not found\n");
 403                return ret;
 404        }
 405        priv->clk_rate = clk_get_periph_rate(clkdev, ret);
 406
 407        /* initialize HW */
 408        pic32_spi_hw_init(priv);
 409
 410        /* set word len */
 411        pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
 412
 413        /* PIC32 SPI controller can automatically drive /CS during transfer
 414         * depending on fifo fill-level. /CS will stay asserted as long as
 415         * TX fifo is non-empty, else will be deasserted confirming completion
 416         * of the ongoing transfer. To avoid this sort of error we will drive
 417         * /CS manually by toggling cs-gpio pins.
 418         */
 419        ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
 420                                         &priv->cs_gpio, GPIOD_IS_OUT);
 421        if (ret) {
 422                printf("pic32-spi: error, cs-gpios not found\n");
 423                return ret;
 424        }
 425
 426        return 0;
 427}
 428
 429static const struct dm_spi_ops pic32_spi_ops = {
 430        .claim_bus      = pic32_spi_claim_bus,
 431        .release_bus    = pic32_spi_release_bus,
 432        .xfer           = pic32_spi_xfer,
 433        .set_speed      = pic32_spi_set_speed,
 434        .set_mode       = pic32_spi_set_mode,
 435        .set_wordlen    = pic32_spi_set_wordlen,
 436};
 437
 438static const struct udevice_id pic32_spi_ids[] = {
 439        { .compatible = "microchip,pic32mzda-spi" },
 440        { }
 441};
 442
 443U_BOOT_DRIVER(pic32_spi) = {
 444        .name           = "pic32_spi",
 445        .id             = UCLASS_SPI,
 446        .of_match       = pic32_spi_ids,
 447        .ops            = &pic32_spi_ops,
 448        .priv_auto      = sizeof(struct pic32_spi_priv),
 449        .probe          = pic32_spi_probe,
 450};
 451