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5
6#include <common.h>
7#include <clk.h>
8#include <display.h>
9#include <dm.h>
10#include <dw_hdmi.h>
11#include <edid.h>
12#include <regmap.h>
13#include <syscon.h>
14#include <asm/gpio.h>
15#include <asm/io.h>
16#include <asm/arch-rockchip/clock.h>
17#include <asm/arch-rockchip/hardware.h>
18#include <asm/arch-rockchip/grf_rk3399.h>
19#include <power/regulator.h>
20#include "rk_hdmi.h"
21
22static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp,
23 const struct display_timing *edid)
24{
25 struct rk_hdmi_priv *priv = dev_get_priv(dev);
26 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
27 int vop_id = uc_plat->source_id;
28 struct rk3399_grf_regs *grf = priv->grf;
29
30
31 rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK,
32 (vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0);
33
34 return dw_hdmi_enable(&priv->hdmi, edid);
35}
36
37static int rk3399_hdmi_of_to_plat(struct udevice *dev)
38{
39 struct rk_hdmi_priv *priv = dev_get_priv(dev);
40 struct dw_hdmi *hdmi = &priv->hdmi;
41
42 hdmi->i2c_clk_high = 0x7a;
43 hdmi->i2c_clk_low = 0x8d;
44
45 return rk_hdmi_of_to_plat(dev);
46}
47
48static const char * const rk3399_regulator_names[] = {
49 "vcc1v8_hdmi",
50 "vcc0v9_hdmi"
51};
52
53static int rk3399_hdmi_probe(struct udevice *dev)
54{
55
56 rk_hdmi_probe_regulators(dev, rk3399_regulator_names,
57 ARRAY_SIZE(rk3399_regulator_names));
58
59 return rk_hdmi_probe(dev);
60}
61
62static const struct dm_display_ops rk3399_hdmi_ops = {
63 .read_edid = rk_hdmi_read_edid,
64 .enable = rk3399_hdmi_enable,
65};
66
67static const struct udevice_id rk3399_hdmi_ids[] = {
68 { .compatible = "rockchip,rk3399-dw-hdmi" },
69 { }
70};
71
72U_BOOT_DRIVER(rk3399_hdmi_rockchip) = {
73 .name = "rk3399_hdmi_rockchip",
74 .id = UCLASS_DISPLAY,
75 .of_match = rk3399_hdmi_ids,
76 .ops = &rk3399_hdmi_ops,
77 .of_to_plat = rk3399_hdmi_of_to_plat,
78 .probe = rk3399_hdmi_probe,
79 .priv_auto = sizeof(struct rk_hdmi_priv),
80};
81