1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef __LS1043AQDS_H__ 7#define __LS1043AQDS_H__ 8 9#include "ls1043a_common.h" 10 11#define CONFIG_LAYERSCAPE_NS_ACCESS 12 13#define CONFIG_DIMM_SLOTS_PER_CTLR 1 14/* Physical Memory Map */ 15#define CONFIG_CHIP_SELECTS_PER_CTRL 4 16 17#define SPD_EEPROM_ADDRESS 0x51 18#define CONFIG_SYS_SPD_BUS_NUM 0 19 20#ifdef CONFIG_DDR_ECC 21#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 22#endif 23 24#ifdef CONFIG_SYS_DPAA_FMAN 25#define RGMII_PHY1_ADDR 0x1 26#define RGMII_PHY2_ADDR 0x2 27#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 28#define SGMII_CARD_PORT2_PHY_ADDR 0x1D 29#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 30#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 31/* PHY address on QSGMII riser card on slot 1 */ 32#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 33#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 34#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 35#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 36/* PHY address on QSGMII riser card on slot 2 */ 37#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 38#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 39#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 40#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 41#endif 42 43/* LPUART */ 44#ifdef CONFIG_LPUART 45#define CONFIG_LPUART_32B_REG 46#endif 47 48/* SATA */ 49 50/* EEPROM */ 51#define CONFIG_SYS_I2C_EEPROM_NXID 52#define CONFIG_SYS_EEPROM_BUS_NUM 0 53 54#define CONFIG_SYS_SATA AHCI_BASE_ADDR 55 56/* 57 * IFC Definitions 58 */ 59#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 60#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 61#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 62 CSPR_PORT_SIZE_16 | \ 63 CSPR_MSEL_NOR | \ 64 CSPR_V) 65#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 66#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 67 + 0x8000000) | \ 68 CSPR_PORT_SIZE_16 | \ 69 CSPR_MSEL_NOR | \ 70 CSPR_V) 71#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 72 73#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 74 CSOR_NOR_TRHZ_80) 75#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 76 FTIM0_NOR_TEADC(0x5) | \ 77 FTIM0_NOR_TEAHC(0x5)) 78#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 79 FTIM1_NOR_TRAD_NOR(0x1a) | \ 80 FTIM1_NOR_TSEQRAD_NOR(0x13)) 81#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 82 FTIM2_NOR_TCH(0x4) | \ 83 FTIM2_NOR_TWPH(0xe) | \ 84 FTIM2_NOR_TWP(0x1c)) 85#define CONFIG_SYS_NOR_FTIM3 0 86 87#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 88#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 89#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 90 91#define CONFIG_SYS_FLASH_EMPTY_INFO 92#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 93 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 94 95#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 96#define CONFIG_SYS_WRITE_SWAPPED_DATA 97 98/* 99 * NAND Flash Definitions 100 */ 101 102#define CONFIG_SYS_NAND_BASE 0x7e800000 103#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 104 105#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 106 107#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 108 | CSPR_PORT_SIZE_8 \ 109 | CSPR_MSEL_NAND \ 110 | CSPR_V) 111#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 112#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 113 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 114 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 115 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 116 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 117 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 118 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 119 120#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 121 FTIM0_NAND_TWP(0x18) | \ 122 FTIM0_NAND_TWCHT(0x7) | \ 123 FTIM0_NAND_TWH(0xa)) 124#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 125 FTIM1_NAND_TWBE(0x39) | \ 126 FTIM1_NAND_TRR(0xe) | \ 127 FTIM1_NAND_TRP(0x18)) 128#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 129 FTIM2_NAND_TREH(0xa) | \ 130 FTIM2_NAND_TWHRE(0x1e)) 131#define CONFIG_SYS_NAND_FTIM3 0x0 132 133#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 134#define CONFIG_SYS_MAX_NAND_DEVICE 1 135#define CONFIG_MTD_NAND_VERIFY_WRITE 136#endif 137 138#ifdef CONFIG_NAND_BOOT 139#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 140#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 141#endif 142 143#if defined(CONFIG_TFABOOT) || \ 144 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 145#define CONFIG_QIXIS_I2C_ACCESS 146#endif 147 148/* 149 * QIXIS Definitions 150 */ 151#define CONFIG_FSL_QIXIS 152 153#ifdef CONFIG_FSL_QIXIS 154#define QIXIS_BASE 0x7fb00000 155#define QIXIS_BASE_PHYS QIXIS_BASE 156#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 157#define QIXIS_LBMAP_SWITCH 6 158#define QIXIS_LBMAP_MASK 0x0f 159#define QIXIS_LBMAP_SHIFT 0 160#define QIXIS_LBMAP_DFLTBANK 0x00 161#define QIXIS_LBMAP_ALTBANK 0x04 162#define QIXIS_LBMAP_NAND 0x09 163#define QIXIS_LBMAP_SD 0x00 164#define QIXIS_LBMAP_SD_QSPI 0xff 165#define QIXIS_LBMAP_QSPI 0xff 166#define QIXIS_RCW_SRC_NAND 0x106 167#define QIXIS_RCW_SRC_SD 0x040 168#define QIXIS_RCW_SRC_QSPI 0x045 169#define QIXIS_RST_CTL_RESET 0x41 170#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 171#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 172#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 173 174#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 175#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 176 CSPR_PORT_SIZE_8 | \ 177 CSPR_MSEL_GPCM | \ 178 CSPR_V) 179#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 180#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 181 CSOR_NOR_NOR_MODE_AVD_NOR | \ 182 CSOR_NOR_TRHZ_80) 183 184/* 185 * QIXIS Timing parameters for IFC GPCM 186 */ 187#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 188 FTIM0_GPCM_TEADC(0x20) | \ 189 FTIM0_GPCM_TEAHC(0x10)) 190#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 191 FTIM1_GPCM_TRAD(0x1f)) 192#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 193 FTIM2_GPCM_TCH(0x8) | \ 194 FTIM2_GPCM_TWP(0xf0)) 195#define CONFIG_SYS_FPGA_FTIM3 0x0 196#endif 197 198#ifdef CONFIG_TFABOOT 199#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 200#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 201#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 202#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 203#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 204#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 205#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 206#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 207#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 208#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 209#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 210#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 211#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 212#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 213#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 214#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 215#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 216#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 217#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 218#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 219#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 220#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 221#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 222#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 223#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 224#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 225#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 226#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 227#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 228#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 229#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 230#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 231#else 232#ifdef CONFIG_NAND_BOOT 233#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 234#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 235#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 236#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 237#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 238#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 239#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 240#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 241#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 242#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 243#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 244#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 245#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 246#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 247#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 248#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 249#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 250#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 251#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 252#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 253#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 254#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 255#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 256#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 257#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 258#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 259#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 260#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 261#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 262#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 263#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 264#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 265#else 266#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 267#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 268#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 269#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 270#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 271#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 272#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 273#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 274#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 275#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 276#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 277#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 278#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 279#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 280#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 281#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 282#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 283#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 284#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 285#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 286#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 287#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 288#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 289#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 290#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 291#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 292#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 293#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 294#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 295#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 296#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 297#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 298#endif 299#endif 300 301/* 302 * I2C bus multiplexer 303 */ 304#define I2C_MUX_PCA_ADDR_PRI 0x77 305#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 306#define I2C_RETIMER_ADDR 0x18 307#define I2C_MUX_CH_DEFAULT 0x8 308#define I2C_MUX_CH_CH7301 0xC 309#define I2C_MUX_CH5 0xD 310#define I2C_MUX_CH7 0xF 311 312#define I2C_MUX_CH_VOL_MONITOR 0xa 313 314/* Voltage monitor on channel 2*/ 315#define I2C_VOL_MONITOR_ADDR 0x40 316#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 317#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 318#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 319 320/* The lowest and highest voltage allowed for LS1043AQDS */ 321#define VDD_MV_MIN 819 322#define VDD_MV_MAX 1212 323 324/* 325 * Miscellaneous configurable options 326 */ 327 328#define CONFIG_SYS_INIT_SP_OFFSET \ 329 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 330 331#ifdef CONFIG_SPL_BUILD 332#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 333#else 334#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 335#endif 336 337/* 338 * Environment 339 */ 340 341#include <asm/fsl_secure_boot.h> 342 343#endif /* __LS1043AQDS_H__ */ 344