1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017, 2019-2021 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7#ifndef __LS2_QDS_H 8#define __LS2_QDS_H 9 10#include "ls2080a_common.h" 11 12#ifdef CONFIG_FSL_QSPI 13#define CONFIG_QIXIS_I2C_ACCESS 14#define CONFIG_SYS_I2C_IFDR_DIV 0x7e 15#endif 16 17#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 18#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) 19 20#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 21#define SPD_EEPROM_ADDRESS1 0x51 22#define SPD_EEPROM_ADDRESS2 0x52 23#define SPD_EEPROM_ADDRESS3 0x53 24#define SPD_EEPROM_ADDRESS4 0x54 25#define SPD_EEPROM_ADDRESS5 0x55 26#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 27#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 28#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 29#define CONFIG_DIMM_SLOTS_PER_CTLR 2 30#define CONFIG_CHIP_SELECTS_PER_CTRL 4 31#ifdef CONFIG_SYS_FSL_HAS_DP_DDR 32#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 33#endif 34 35/* SATA */ 36 37#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 38#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 39 40#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 41#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 42#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 43 44#define CONFIG_SYS_NOR0_CSPR \ 45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 46 CSPR_PORT_SIZE_16 | \ 47 CSPR_MSEL_NOR | \ 48 CSPR_V) 49#define CONFIG_SYS_NOR0_CSPR_EARLY \ 50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 51 CSPR_PORT_SIZE_16 | \ 52 CSPR_MSEL_NOR | \ 53 CSPR_V) 54#define CONFIG_SYS_NOR1_CSPR \ 55 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 56 CSPR_PORT_SIZE_16 | \ 57 CSPR_MSEL_NOR | \ 58 CSPR_V) 59#define CONFIG_SYS_NOR1_CSPR_EARLY \ 60 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 61 CSPR_PORT_SIZE_16 | \ 62 CSPR_MSEL_NOR | \ 63 CSPR_V) 64#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 65#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 66 FTIM0_NOR_TEADC(0x5) | \ 67 FTIM0_NOR_TEAHC(0x5)) 68#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 69 FTIM1_NOR_TRAD_NOR(0x1a) |\ 70 FTIM1_NOR_TSEQRAD_NOR(0x13)) 71#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 72 FTIM2_NOR_TCH(0x4) | \ 73 FTIM2_NOR_TWPH(0x0E) | \ 74 FTIM2_NOR_TWP(0x1c)) 75#define CONFIG_SYS_NOR_FTIM3 0x04000000 76#define CONFIG_SYS_IFC_CCR 0x01000000 77 78#ifdef CONFIG_MTD_NOR_FLASH 79#define CONFIG_SYS_FLASH_QUIET_TEST 80#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 81 82#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 83#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 84#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 85 86#define CONFIG_SYS_FLASH_EMPTY_INFO 87#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 88 CONFIG_SYS_FLASH_BASE + 0x40000000} 89#endif 90 91#define CONFIG_SYS_NAND_MAX_ECCPOS 256 92#define CONFIG_SYS_NAND_MAX_OOBFREE 2 93 94#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 95#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 96 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 97 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 98 | CSPR_V) 99#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 100 101#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 102 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 103 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 104 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 105 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 106 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 107 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 108 109/* ONFI NAND Flash mode0 Timing Params */ 110#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 111 FTIM0_NAND_TWP(0x18) | \ 112 FTIM0_NAND_TWCHT(0x07) | \ 113 FTIM0_NAND_TWH(0x0a)) 114#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 115 FTIM1_NAND_TWBE(0x39) | \ 116 FTIM1_NAND_TRR(0x0e) | \ 117 FTIM1_NAND_TRP(0x18)) 118#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 119 FTIM2_NAND_TREH(0x0a) | \ 120 FTIM2_NAND_TWHRE(0x1e)) 121#define CONFIG_SYS_NAND_FTIM3 0x0 122 123#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 124#define CONFIG_SYS_MAX_NAND_DEVICE 1 125#define CONFIG_MTD_NAND_VERIFY_WRITE 126 127#define CONFIG_FSL_QIXIS /* use common QIXIS code */ 128#define QIXIS_LBMAP_SWITCH 0x06 129#define QIXIS_LBMAP_MASK 0x0f 130#define QIXIS_LBMAP_SHIFT 0 131#define QIXIS_LBMAP_DFLTBANK 0x00 132#define QIXIS_LBMAP_ALTBANK 0x04 133#define QIXIS_LBMAP_NAND 0x09 134#define QIXIS_LBMAP_SD 0x00 135#define QIXIS_LBMAP_QSPI 0x0f 136#define QIXIS_RST_CTL_RESET 0x31 137#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 138#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 139#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 140#define QIXIS_RCW_SRC_NAND 0x107 141#define QIXIS_RCW_SRC_SD 0x40 142#define QIXIS_RCW_SRC_QSPI 0x62 143#define QIXIS_RST_FORCE_MEM 0x01 144 145#define CONFIG_SYS_CSPR3_EXT (0x0) 146#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 147 | CSPR_PORT_SIZE_8 \ 148 | CSPR_MSEL_GPCM \ 149 | CSPR_V) 150#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 151 | CSPR_PORT_SIZE_8 \ 152 | CSPR_MSEL_GPCM \ 153 | CSPR_V) 154 155#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 156#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 157/* QIXIS Timing parameters for IFC CS3 */ 158#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 159 FTIM0_GPCM_TEADC(0x0e) | \ 160 FTIM0_GPCM_TEAHC(0x0e)) 161#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 162 FTIM1_GPCM_TRAD(0x3f)) 163#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 164 FTIM2_GPCM_TCH(0xf) | \ 165 FTIM2_GPCM_TWP(0x3E)) 166#define CONFIG_SYS_CS3_FTIM3 0x0 167 168#if defined(CONFIG_SPL) 169#if defined(CONFIG_NAND_BOOT) 170#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 171#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 172#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 173#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 174#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 175#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 176#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 177#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 178#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 179#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 180#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 181#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 182#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 183#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 184#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 185#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 186#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 187#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 188#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 189#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 190#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 191#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 192#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 193#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 194#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 195#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 196#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 197 198#define CONFIG_SPL_PAD_TO 0x20000 199#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 200#endif 201#else 202#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 203#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 204#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 205#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 206#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 207#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 208#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 209#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 210#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 211#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 212#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 213#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 214#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 215#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 216#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 217#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 218#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 219#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 220#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 221#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 222#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 223#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 224#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 225#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 226#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 227#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 228#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 229#endif 230 231/* Debug Server firmware */ 232#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 233#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 234 235#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 236 237/* 238 * I2C 239 */ 240#define I2C_MUX_PCA_ADDR 0x77 241#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 242 243/* I2C bus multiplexer */ 244#define I2C_MUX_CH_DEFAULT 0x8 245 246/* SPI */ 247 248/* 249 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 250 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 251 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 252 */ 253#define FSL_QIXIS_BRDCFG9_QSPI 0x1 254 255/* 256 * MMC 257 */ 258#ifdef CONFIG_MMC 259#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 260 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 261#endif 262 263/* 264 * RTC configuration 265 */ 266#define RTC 267#define CONFIG_RTC_DS3231 1 268#define CONFIG_SYS_I2C_RTC_ADDR 0x68 269 270/* EEPROM */ 271#define CONFIG_SYS_I2C_EEPROM_NXID 272#define CONFIG_SYS_EEPROM_BUS_NUM 0 273 274#define CONFIG_FSL_MEMAC 275 276#ifdef CONFIG_PCI 277#define CONFIG_PCI_SCAN_SHOW 278#endif 279 280/* Initial environment variables */ 281#undef CONFIG_EXTRA_ENV_SETTINGS 282#ifdef CONFIG_NXP_ESBC 283#define CONFIG_EXTRA_ENV_SETTINGS \ 284 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 285 "loadaddr=0x80100000\0" \ 286 "kernel_addr=0x100000\0" \ 287 "ramdisk_addr=0x800000\0" \ 288 "ramdisk_size=0x2000000\0" \ 289 "fdt_high=0xa0000000\0" \ 290 "initrd_high=0xffffffffffffffff\0" \ 291 "kernel_start=0x581000000\0" \ 292 "kernel_load=0xa0000000\0" \ 293 "kernel_size=0x2800000\0" \ 294 "mcmemsize=0x40000000\0" \ 295 "mcinitcmd=esbc_validate 0x580640000;" \ 296 "esbc_validate 0x580680000;" \ 297 "fsl_mc start mc 0x580a00000" \ 298 " 0x580e00000 \0" 299#else 300#ifdef CONFIG_TFABOOT 301#define SD_MC_INIT_CMD \ 302 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ 303 "mmc read 0x80e00000 0x7000 0x800;" \ 304 "fsl_mc start mc 0x80a00000 0x80e00000\0" 305#define IFC_MC_INIT_CMD \ 306 "fsl_mc start mc 0x580a00000" \ 307 " 0x580e00000 \0" 308#define CONFIG_EXTRA_ENV_SETTINGS \ 309 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 310 "loadaddr=0x80100000\0" \ 311 "loadaddr_sd=0x90100000\0" \ 312 "kernel_addr=0x581000000\0" \ 313 "kernel_addr_sd=0x8000\0" \ 314 "ramdisk_addr=0x800000\0" \ 315 "ramdisk_size=0x2000000\0" \ 316 "fdt_high=0xa0000000\0" \ 317 "initrd_high=0xffffffffffffffff\0" \ 318 "kernel_start=0x581000000\0" \ 319 "kernel_start_sd=0x8000\0" \ 320 "kernel_load=0xa0000000\0" \ 321 "kernel_size=0x2800000\0" \ 322 "kernel_size_sd=0x14000\0" \ 323 "load_addr=0xa0000000\0" \ 324 "kernelheader_addr=0x580600000\0" \ 325 "kernelheader_addr_r=0x80200000\0" \ 326 "kernelheader_size=0x40000\0" \ 327 "BOARD=ls2088aqds\0" \ 328 "mcmemsize=0x70000000 \0" \ 329 "scriptaddr=0x80000000\0" \ 330 "scripthdraddr=0x80080000\0" \ 331 IFC_MC_INIT_CMD \ 332 BOOTENV \ 333 "boot_scripts=ls2088aqds_boot.scr\0" \ 334 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ 335 "scan_dev_for_boot_part=" \ 336 "part list ${devtype} ${devnum} devplist; " \ 337 "env exists devplist || setenv devplist 1; " \ 338 "for distro_bootpart in ${devplist}; do " \ 339 "if fstype ${devtype} " \ 340 "${devnum}:${distro_bootpart} " \ 341 "bootfstype; then " \ 342 "run scan_dev_for_boot; " \ 343 "fi; " \ 344 "done\0" \ 345 "boot_a_script=" \ 346 "load ${devtype} ${devnum}:${distro_bootpart} " \ 347 "${scriptaddr} ${prefix}${script}; " \ 348 "env exists secureboot && load ${devtype} " \ 349 "${devnum}:${distro_bootpart} " \ 350 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 351 "&& esbc_validate ${scripthdraddr};" \ 352 "source ${scriptaddr}\0" \ 353 "nor_bootcmd=echo Trying load from nor..;" \ 354 "cp.b $kernel_addr $load_addr " \ 355 "$kernel_size ; env exists secureboot && " \ 356 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 357 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 358 "bootm $load_addr#$BOARD\0" \ 359 "sd_bootcmd=echo Trying load from SD ..;" \ 360 "mmcinfo; mmc read $load_addr " \ 361 "$kernel_addr_sd $kernel_size_sd && " \ 362 "bootm $load_addr#$BOARD\0" 363#elif defined(CONFIG_SD_BOOT) 364#define CONFIG_EXTRA_ENV_SETTINGS \ 365 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 366 "loadaddr=0x90100000\0" \ 367 "kernel_addr=0x800\0" \ 368 "ramdisk_addr=0x800000\0" \ 369 "ramdisk_size=0x2000000\0" \ 370 "fdt_high=0xa0000000\0" \ 371 "initrd_high=0xffffffffffffffff\0" \ 372 "kernel_start=0x8000\0" \ 373 "kernel_load=0xa0000000\0" \ 374 "kernel_size=0x14000\0" \ 375 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ 376 "mmc read 0x80e00000 0x7000 0x800;" \ 377 "fsl_mc start mc 0x80a00000 0x80e00000\0" \ 378 "mcmemsize=0x70000000 \0" 379#else 380#define CONFIG_EXTRA_ENV_SETTINGS \ 381 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 382 "loadaddr=0x80100000\0" \ 383 "kernel_addr=0x100000\0" \ 384 "ramdisk_addr=0x800000\0" \ 385 "ramdisk_size=0x2000000\0" \ 386 "fdt_high=0xa0000000\0" \ 387 "initrd_high=0xffffffffffffffff\0" \ 388 "kernel_start=0x581000000\0" \ 389 "kernel_load=0xa0000000\0" \ 390 "kernel_size=0x2800000\0" \ 391 "mcmemsize=0x40000000\0" \ 392 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 393 " 0x580e00000 \0" 394#endif /* CONFIG_TFABOOT */ 395#endif /* CONFIG_NXP_ESBC */ 396 397#ifdef CONFIG_TFABOOT 398#define BOOT_TARGET_DEVICES(func) \ 399 func(USB, usb, 0) \ 400 func(MMC, mmc, 0) \ 401 func(SCSI, scsi, 0) \ 402 func(DHCP, dhcp, na) 403#include <config_distro_bootcmd.h> 404 405#define SD_BOOTCOMMAND \ 406 "env exists mcinitcmd && env exists secureboot "\ 407 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ 408 "&& esbc_validate $load_addr; " \ 409 "env exists mcinitcmd && run mcinitcmd " \ 410 "&& mmc read 0x80d00000 0x6800 0x800 " \ 411 "&& fsl_mc lazyapply dpl 0x80d00000; " \ 412 "run distro_bootcmd;run sd_bootcmd; " \ 413 "env exists secureboot && esbc_halt;" 414 415#define IFC_NOR_BOOTCOMMAND \ 416 "env exists mcinitcmd && env exists secureboot "\ 417 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ 418 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 419 "run distro_bootcmd;run nor_bootcmd; " \ 420 "env exists secureboot && esbc_halt;" 421#endif 422 423#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 424#define CONFIG_FSL_MEMAC 425#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 426#define SGMII_CARD_PORT2_PHY_ADDR 0x1d 427#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 428#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 429 430#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 431#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 432#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 433#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 434#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 435#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 436#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 437#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 438#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 439#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 440#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 441#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 442#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 443#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 444#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 445#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 446 447#define CONFIG_ETHPRIME "DPMAC1@xgmii" 448 449#endif 450 451#include <asm/fsl_secure_boot.h> 452 453#endif /* __LS2_QDS_H */ 454