1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 9 10/* pmucru-clocks indices */ 11 12/* pmucru plls */ 13#define PLL_PPLL 1 14#define PLL_HPLL 2 15 16/* pmucru clocks */ 17#define XIN_OSC0_DIV 4 18#define CLK_RTC_32K 5 19#define CLK_PMU 6 20#define CLK_I2C0 7 21#define CLK_RTC32K_FRAC 8 22#define CLK_UART0_DIV 9 23#define CLK_UART0_FRAC 10 24#define SCLK_UART0 11 25#define DBCLK_GPIO0 12 26#define CLK_PWM0 13 27#define CLK_CAPTURE_PWM0_NDFT 14 28#define CLK_PMUPVTM 15 29#define CLK_CORE_PMUPVTM 16 30#define CLK_REF24M 17 31#define XIN_OSC0_USBPHY0_G 18 32#define CLK_USBPHY0_REF 19 33#define XIN_OSC0_USBPHY1_G 20 34#define CLK_USBPHY1_REF 21 35#define XIN_OSC0_MIPIDSIPHY0_G 22 36#define CLK_MIPIDSIPHY0_REF 23 37#define XIN_OSC0_MIPIDSIPHY1_G 24 38#define CLK_MIPIDSIPHY1_REF 25 39#define CLK_WIFI_DIV 26 40#define CLK_WIFI_OSC0 27 41#define CLK_WIFI 28 42#define CLK_PCIEPHY0_DIV 29 43#define CLK_PCIEPHY0_OSC0 30 44#define CLK_PCIEPHY0_REF 31 45#define CLK_PCIEPHY1_DIV 32 46#define CLK_PCIEPHY1_OSC0 33 47#define CLK_PCIEPHY1_REF 34 48#define CLK_PCIEPHY2_DIV 35 49#define CLK_PCIEPHY2_OSC0 36 50#define CLK_PCIEPHY2_REF 37 51#define CLK_PCIE30PHY_REF_M 38 52#define CLK_PCIE30PHY_REF_N 39 53#define CLK_HDMI_REF 40 54#define XIN_OSC0_EDPPHY_G 41 55#define PCLK_PDPMU 42 56#define PCLK_PMU 43 57#define PCLK_UART0 44 58#define PCLK_I2C0 45 59#define PCLK_GPIO0 46 60#define PCLK_PMUPVTM 47 61#define PCLK_PWM0 48 62#define CLK_PDPMU 49 63#define SCLK_32K_IOE 50 64 65#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) 66 67/* cru-clocks indices */ 68 69/* cru plls */ 70#define PLL_APLL 1 71#define PLL_DPLL 2 72#define PLL_CPLL 3 73#define PLL_GPLL 4 74#define PLL_VPLL 5 75#define PLL_NPLL 6 76 77/* cru clocks */ 78#define CPLL_333M 9 79#define ARMCLK 10 80#define USB480M 11 81#define ACLK_CORE_NIU2BUS 18 82#define CLK_CORE_PVTM 19 83#define CLK_CORE_PVTM_CORE 20 84#define CLK_CORE_PVTPLL 21 85#define CLK_GPU_SRC 22 86#define CLK_GPU_PRE_NDFT 23 87#define CLK_GPU_PRE_MUX 24 88#define ACLK_GPU_PRE 25 89#define PCLK_GPU_PRE 26 90#define CLK_GPU 27 91#define CLK_GPU_NP5 28 92#define PCLK_GPU_PVTM 29 93#define CLK_GPU_PVTM 30 94#define CLK_GPU_PVTM_CORE 31 95#define CLK_GPU_PVTPLL 32 96#define CLK_NPU_SRC 33 97#define CLK_NPU_PRE_NDFT 34 98#define CLK_NPU 35 99#define CLK_NPU_NP5 36 100#define HCLK_NPU_PRE 37 101#define PCLK_NPU_PRE 38 102#define ACLK_NPU_PRE 39 103#define ACLK_NPU 40 104#define HCLK_NPU 41 105#define PCLK_NPU_PVTM 42 106#define CLK_NPU_PVTM 43 107#define CLK_NPU_PVTM_CORE 44 108#define CLK_NPU_PVTPLL 45 109#define CLK_DDRPHY1X_SRC 46 110#define CLK_DDRPHY1X_HWFFC_SRC 47 111#define CLK_DDR1X 48 112#define CLK_MSCH 49 113#define CLK24_DDRMON 50 114#define ACLK_GIC_AUDIO 51 115#define HCLK_GIC_AUDIO 52 116#define HCLK_SDMMC_BUFFER 53 117#define DCLK_SDMMC_BUFFER 54 118#define ACLK_GIC600 55 119#define ACLK_SPINLOCK 56 120#define HCLK_I2S0_8CH 57 121#define HCLK_I2S1_8CH 58 122#define HCLK_I2S2_2CH 59 123#define HCLK_I2S3_2CH 60 124#define CLK_I2S0_8CH_TX_SRC 61 125#define CLK_I2S0_8CH_TX_FRAC 62 126#define MCLK_I2S0_8CH_TX 63 127#define I2S0_MCLKOUT_TX 64 128#define CLK_I2S0_8CH_RX_SRC 65 129#define CLK_I2S0_8CH_RX_FRAC 66 130#define MCLK_I2S0_8CH_RX 67 131#define I2S0_MCLKOUT_RX 68 132#define CLK_I2S1_8CH_TX_SRC 69 133#define CLK_I2S1_8CH_TX_FRAC 70 134#define MCLK_I2S1_8CH_TX 71 135#define I2S1_MCLKOUT_TX 72 136#define CLK_I2S1_8CH_RX_SRC 73 137#define CLK_I2S1_8CH_RX_FRAC 74 138#define MCLK_I2S1_8CH_RX 75 139#define I2S1_MCLKOUT_RX 76 140#define CLK_I2S2_2CH_SRC 77 141#define CLK_I2S2_2CH_FRAC 78 142#define MCLK_I2S2_2CH 79 143#define I2S2_MCLKOUT 80 144#define CLK_I2S3_2CH_TX_SRC 81 145#define CLK_I2S3_2CH_TX_FRAC 82 146#define MCLK_I2S3_2CH_TX 83 147#define I2S3_MCLKOUT_TX 84 148#define CLK_I2S3_2CH_RX_SRC 85 149#define CLK_I2S3_2CH_RX_FRAC 86 150#define MCLK_I2S3_2CH_RX 87 151#define I2S3_MCLKOUT_RX 88 152#define HCLK_PDM 89 153#define MCLK_PDM 90 154#define HCLK_VAD 91 155#define HCLK_SPDIF_8CH 92 156#define MCLK_SPDIF_8CH_SRC 93 157#define MCLK_SPDIF_8CH_FRAC 94 158#define MCLK_SPDIF_8CH 95 159#define HCLK_AUDPWM 96 160#define SCLK_AUDPWM_SRC 97 161#define SCLK_AUDPWM_FRAC 98 162#define SCLK_AUDPWM 99 163#define HCLK_ACDCDIG 100 164#define CLK_ACDCDIG_I2C 101 165#define CLK_ACDCDIG_DAC 102 166#define CLK_ACDCDIG_ADC 103 167#define ACLK_SECURE_FLASH 104 168#define HCLK_SECURE_FLASH 105 169#define ACLK_CRYPTO_NS 106 170#define HCLK_CRYPTO_NS 107 171#define CLK_CRYPTO_NS_CORE 108 172#define CLK_CRYPTO_NS_PKA 109 173#define CLK_CRYPTO_NS_RNG 110 174#define HCLK_TRNG_NS 111 175#define CLK_TRNG_NS 112 176#define PCLK_OTPC_NS 113 177#define CLK_OTPC_NS_SBPI 114 178#define CLK_OTPC_NS_USR 115 179#define HCLK_NANDC 116 180#define NCLK_NANDC 117 181#define HCLK_SFC 118 182#define HCLK_SFC_XIP 119 183#define SCLK_SFC 120 184#define ACLK_EMMC 121 185#define HCLK_EMMC 122 186#define BCLK_EMMC 123 187#define CCLK_EMMC 124 188#define TCLK_EMMC 125 189#define ACLK_PIPE 126 190#define PCLK_PIPE 127 191#define PCLK_PIPE_GRF 128 192#define ACLK_PCIE20_MST 129 193#define ACLK_PCIE20_SLV 130 194#define ACLK_PCIE20_DBI 131 195#define PCLK_PCIE20 132 196#define CLK_PCIE20_AUX_NDFT 133 197#define CLK_PCIE20_AUX_DFT 134 198#define CLK_PCIE20_PIPE_DFT 135 199#define ACLK_PCIE30X1_MST 136 200#define ACLK_PCIE30X1_SLV 137 201#define ACLK_PCIE30X1_DBI 138 202#define PCLK_PCIE30X1 139 203#define CLK_PCIE30X1_AUX_NDFT 140 204#define CLK_PCIE30X1_AUX_DFT 141 205#define CLK_PCIE30X1_PIPE_DFT 142 206#define ACLK_PCIE30X2_MST 143 207#define ACLK_PCIE30X2_SLV 144 208#define ACLK_PCIE30X2_DBI 145 209#define PCLK_PCIE30X2 146 210#define CLK_PCIE30X2_AUX_NDFT 147 211#define CLK_PCIE30X2_AUX_DFT 148 212#define CLK_PCIE30X2_PIPE_DFT 149 213#define ACLK_SATA0 150 214#define CLK_SATA0_PMALIVE 151 215#define CLK_SATA0_RXOOB 152 216#define CLK_SATA0_PIPE_NDFT 153 217#define CLK_SATA0_PIPE_DFT 154 218#define ACLK_SATA1 155 219#define CLK_SATA1_PMALIVE 156 220#define CLK_SATA1_RXOOB 157 221#define CLK_SATA1_PIPE_NDFT 158 222#define CLK_SATA1_PIPE_DFT 159 223#define ACLK_SATA2 160 224#define CLK_SATA2_PMALIVE 161 225#define CLK_SATA2_RXOOB 162 226#define CLK_SATA2_PIPE_NDFT 163 227#define CLK_SATA2_PIPE_DFT 164 228#define ACLK_USB3OTG0 165 229#define CLK_USB3OTG0_REF 166 230#define CLK_USB3OTG0_SUSPEND 167 231#define ACLK_USB3OTG1 168 232#define CLK_USB3OTG1_REF 169 233#define CLK_USB3OTG1_SUSPEND 170 234#define CLK_XPCS_EEE 171 235#define PCLK_XPCS 172 236#define ACLK_PHP 173 237#define HCLK_PHP 174 238#define PCLK_PHP 175 239#define HCLK_SDMMC0 176 240#define CLK_SDMMC0 177 241#define HCLK_SDMMC1 178 242#define CLK_SDMMC1 179 243#define ACLK_GMAC0 180 244#define PCLK_GMAC0 181 245#define CLK_MAC0_2TOP 182 246#define CLK_MAC0_OUT 183 247#define CLK_MAC0_REFOUT 184 248#define CLK_GMAC0_PTP_REF 185 249#define ACLK_USB 186 250#define HCLK_USB 187 251#define PCLK_USB 188 252#define HCLK_USB2HOST0 189 253#define HCLK_USB2HOST0_ARB 190 254#define HCLK_USB2HOST1 191 255#define HCLK_USB2HOST1_ARB 192 256#define HCLK_SDMMC2 193 257#define CLK_SDMMC2 194 258#define ACLK_GMAC1 195 259#define PCLK_GMAC1 196 260#define CLK_MAC1_2TOP 197 261#define CLK_MAC1_OUT 198 262#define CLK_MAC1_REFOUT 199 263#define CLK_GMAC1_PTP_REF 200 264#define ACLK_PERIMID 201 265#define HCLK_PERIMID 202 266#define ACLK_VI 203 267#define HCLK_VI 204 268#define PCLK_VI 205 269#define ACLK_VICAP 206 270#define HCLK_VICAP 207 271#define DCLK_VICAP 208 272#define ICLK_VICAP_G 209 273#define ACLK_ISP 210 274#define HCLK_ISP 211 275#define CLK_ISP 212 276#define PCLK_CSI2HOST1 213 277#define CLK_CIF_OUT 214 278#define CLK_CAM0_OUT 215 279#define CLK_CAM1_OUT 216 280#define ACLK_VO 217 281#define HCLK_VO 218 282#define PCLK_VO 219 283#define ACLK_VOP_PRE 220 284#define ACLK_VOP 221 285#define HCLK_VOP 222 286#define DCLK_VOP0 223 287#define DCLK_VOP1 224 288#define DCLK_VOP2 225 289#define CLK_VOP_PWM 226 290#define ACLK_HDCP 227 291#define HCLK_HDCP 228 292#define PCLK_HDCP 229 293#define PCLK_HDMI_HOST 230 294#define CLK_HDMI_SFR 231 295#define PCLK_DSITX_0 232 296#define PCLK_DSITX_1 233 297#define PCLK_EDP_CTRL 234 298#define CLK_EDP_200M 235 299#define ACLK_VPU_PRE 236 300#define HCLK_VPU_PRE 237 301#define ACLK_VPU 238 302#define HCLK_VPU 239 303#define ACLK_RGA_PRE 240 304#define HCLK_RGA_PRE 241 305#define PCLK_RGA_PRE 242 306#define ACLK_RGA 243 307#define HCLK_RGA 244 308#define CLK_RGA_CORE 245 309#define ACLK_IEP 246 310#define HCLK_IEP 247 311#define CLK_IEP_CORE 248 312#define HCLK_EBC 249 313#define DCLK_EBC 250 314#define ACLK_JDEC 251 315#define HCLK_JDEC 252 316#define ACLK_JENC 253 317#define HCLK_JENC 254 318#define PCLK_EINK 255 319#define HCLK_EINK 256 320#define ACLK_RKVENC_PRE 257 321#define HCLK_RKVENC_PRE 258 322#define ACLK_RKVENC 259 323#define HCLK_RKVENC 260 324#define CLK_RKVENC_CORE 261 325#define ACLK_RKVDEC_PRE 262 326#define HCLK_RKVDEC_PRE 263 327#define ACLK_RKVDEC 264 328#define HCLK_RKVDEC 265 329#define CLK_RKVDEC_CA 266 330#define CLK_RKVDEC_CORE 267 331#define CLK_RKVDEC_HEVC_CA 268 332#define ACLK_BUS 269 333#define PCLK_BUS 270 334#define PCLK_TSADC 271 335#define CLK_TSADC_TSEN 272 336#define CLK_TSADC 273 337#define PCLK_SARADC 274 338#define CLK_SARADC 275 339#define PCLK_SCR 276 340#define PCLK_WDT_NS 277 341#define TCLK_WDT_NS 278 342#define ACLK_DMAC0 279 343#define ACLK_DMAC1 280 344#define ACLK_MCU 281 345#define PCLK_INTMUX 282 346#define PCLK_MAILBOX 283 347#define PCLK_UART1 284 348#define CLK_UART1_SRC 285 349#define CLK_UART1_FRAC 286 350#define SCLK_UART1 287 351#define PCLK_UART2 288 352#define CLK_UART2_SRC 289 353#define CLK_UART2_FRAC 290 354#define SCLK_UART2 291 355#define PCLK_UART3 292 356#define CLK_UART3_SRC 293 357#define CLK_UART3_FRAC 294 358#define SCLK_UART3 295 359#define PCLK_UART4 296 360#define CLK_UART4_SRC 297 361#define CLK_UART4_FRAC 298 362#define SCLK_UART4 299 363#define PCLK_UART5 300 364#define CLK_UART5_SRC 301 365#define CLK_UART5_FRAC 302 366#define SCLK_UART5 303 367#define PCLK_UART6 304 368#define CLK_UART6_SRC 305 369#define CLK_UART6_FRAC 306 370#define SCLK_UART6 307 371#define PCLK_UART7 308 372#define CLK_UART7_SRC 309 373#define CLK_UART7_FRAC 310 374#define SCLK_UART7 311 375#define PCLK_UART8 312 376#define CLK_UART8_SRC 313 377#define CLK_UART8_FRAC 314 378#define SCLK_UART8 315 379#define PCLK_UART9 316 380#define CLK_UART9_SRC 317 381#define CLK_UART9_FRAC 318 382#define SCLK_UART9 319 383#define PCLK_CAN0 320 384#define CLK_CAN0 321 385#define PCLK_CAN1 322 386#define CLK_CAN1 323 387#define PCLK_CAN2 324 388#define CLK_CAN2 325 389#define CLK_I2C 326 390#define PCLK_I2C1 327 391#define CLK_I2C1 328 392#define PCLK_I2C2 329 393#define CLK_I2C2 330 394#define PCLK_I2C3 331 395#define CLK_I2C3 332 396#define PCLK_I2C4 333 397#define CLK_I2C4 334 398#define PCLK_I2C5 335 399#define CLK_I2C5 336 400#define PCLK_SPI0 337 401#define CLK_SPI0 338 402#define PCLK_SPI1 339 403#define CLK_SPI1 340 404#define PCLK_SPI2 341 405#define CLK_SPI2 342 406#define PCLK_SPI3 343 407#define CLK_SPI3 344 408#define PCLK_PWM1 345 409#define CLK_PWM1 346 410#define CLK_PWM1_CAPTURE 347 411#define PCLK_PWM2 348 412#define CLK_PWM2 349 413#define CLK_PWM2_CAPTURE 350 414#define PCLK_PWM3 351 415#define CLK_PWM3 352 416#define CLK_PWM3_CAPTURE 353 417#define DBCLK_GPIO 354 418#define PCLK_GPIO1 355 419#define DBCLK_GPIO1 356 420#define PCLK_GPIO2 357 421#define DBCLK_GPIO2 358 422#define PCLK_GPIO3 359 423#define DBCLK_GPIO3 360 424#define PCLK_GPIO4 361 425#define DBCLK_GPIO4 362 426#define OCC_SCAN_CLK_GPIO 363 427#define PCLK_TIMER 364 428#define CLK_TIMER0 365 429#define CLK_TIMER1 366 430#define CLK_TIMER2 367 431#define CLK_TIMER3 368 432#define CLK_TIMER4 369 433#define CLK_TIMER5 370 434#define ACLK_TOP_HIGH 371 435#define ACLK_TOP_LOW 372 436#define HCLK_TOP 373 437#define PCLK_TOP 374 438#define PCLK_PCIE30PHY 375 439#define CLK_OPTC_ARB 376 440#define PCLK_MIPICSIPHY 377 441#define PCLK_MIPIDSIPHY0 378 442#define PCLK_MIPIDSIPHY1 379 443#define PCLK_PIPEPHY0 380 444#define PCLK_PIPEPHY1 381 445#define PCLK_PIPEPHY2 382 446#define PCLK_CPU_BOOST 383 447#define CLK_CPU_BOOST 384 448#define PCLK_OTPPHY 385 449#define SCLK_GMAC0 386 450#define SCLK_GMAC0_RGMII_SPEED 387 451#define SCLK_GMAC0_RMII_SPEED 388 452#define SCLK_GMAC0_RX_TX 389 453#define SCLK_GMAC1 390 454#define SCLK_GMAC1_RGMII_SPEED 391 455#define SCLK_GMAC1_RMII_SPEED 392 456#define SCLK_GMAC1_RX_TX 393 457#define SCLK_SDMMC0_DRV 394 458#define SCLK_SDMMC0_SAMPLE 395 459#define SCLK_SDMMC1_DRV 396 460#define SCLK_SDMMC1_SAMPLE 397 461#define SCLK_SDMMC2_DRV 398 462#define SCLK_SDMMC2_SAMPLE 399 463#define SCLK_EMMC_DRV 400 464#define SCLK_EMMC_SAMPLE 401 465#define PCLK_EDPPHY_GRF 402 466#define CLK_HDMI_CEC 403 467#define CLK_I2S0_8CH_TX 404 468#define CLK_I2S0_8CH_RX 405 469#define CLK_I2S1_8CH_TX 406 470#define CLK_I2S1_8CH_RX 407 471#define CLK_I2S2_2CH 408 472#define CLK_I2S3_2CH_TX 409 473#define CLK_I2S3_2CH_RX 410 474#define CPLL_500M 411 475#define CPLL_250M 412 476#define CPLL_125M 413 477#define CPLL_62P5M 414 478#define CPLL_50M 415 479#define CPLL_25M 416 480#define CPLL_100M 417 481 482#define PCLK_CORE_PVTM 450 483 484#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) 485 486/* pmu soft-reset indices */ 487/* pmucru_softrst_con0 */ 488#define SRST_P_PDPMU_NIU 0 489#define SRST_P_PMUCRU 1 490#define SRST_P_PMUGRF 2 491#define SRST_P_I2C0 3 492#define SRST_I2C0 4 493#define SRST_P_UART0 5 494#define SRST_S_UART0 6 495#define SRST_P_PWM0 7 496#define SRST_PWM0 8 497#define SRST_P_GPIO0 9 498#define SRST_GPIO0 10 499#define SRST_P_PMUPVTM 11 500#define SRST_PMUPVTM 12 501 502/* soft-reset indices */ 503 504/* cru_softrst_con0 */ 505#define SRST_NCORERESET0 0 506#define SRST_NCORERESET1 1 507#define SRST_NCORERESET2 2 508#define SRST_NCORERESET3 3 509#define SRST_NCPUPORESET0 4 510#define SRST_NCPUPORESET1 5 511#define SRST_NCPUPORESET2 6 512#define SRST_NCPUPORESET3 7 513#define SRST_NSRESET 8 514#define SRST_NSPORESET 9 515#define SRST_NATRESET 10 516#define SRST_NGICRESET 11 517#define SRST_NPRESET 12 518#define SRST_NPERIPHRESET 13 519 520/* cru_softrst_con1 */ 521#define SRST_A_CORE_NIU2DDR 16 522#define SRST_A_CORE_NIU2BUS 17 523#define SRST_P_DBG_NIU 18 524#define SRST_P_DBG 19 525#define SRST_P_DBG_DAPLITE 20 526#define SRST_DAP 21 527#define SRST_A_ADB400_CORE2GIC 22 528#define SRST_A_ADB400_GIC2CORE 23 529#define SRST_P_CORE_GRF 24 530#define SRST_P_CORE_PVTM 25 531#define SRST_CORE_PVTM 26 532#define SRST_CORE_PVTPLL 27 533 534/* cru_softrst_con2 */ 535#define SRST_GPU 32 536#define SRST_A_GPU_NIU 33 537#define SRST_P_GPU_NIU 34 538#define SRST_P_GPU_PVTM 35 539#define SRST_GPU_PVTM 36 540#define SRST_GPU_PVTPLL 37 541#define SRST_A_NPU_NIU 40 542#define SRST_H_NPU_NIU 41 543#define SRST_P_NPU_NIU 42 544#define SRST_A_NPU 43 545#define SRST_H_NPU 44 546#define SRST_P_NPU_PVTM 45 547#define SRST_NPU_PVTM 46 548#define SRST_NPU_PVTPLL 47 549 550/* cru_softrst_con3 */ 551#define SRST_A_MSCH 51 552#define SRST_HWFFC_CTRL 52 553#define SRST_DDR_ALWAYSON 53 554#define SRST_A_DDRSPLIT 54 555#define SRST_DDRDFI_CTL 55 556#define SRST_A_DMA2DDR 57 557 558/* cru_softrst_con4 */ 559#define SRST_A_PERIMID_NIU 64 560#define SRST_H_PERIMID_NIU 65 561#define SRST_A_GIC_AUDIO_NIU 66 562#define SRST_H_GIC_AUDIO_NIU 67 563#define SRST_A_GIC600 68 564#define SRST_A_GIC600_DEBUG 69 565#define SRST_A_GICADB_CORE2GIC 70 566#define SRST_A_GICADB_GIC2CORE 71 567#define SRST_A_SPINLOCK 72 568#define SRST_H_SDMMC_BUFFER 73 569#define SRST_D_SDMMC_BUFFER 74 570#define SRST_H_I2S0_8CH 75 571#define SRST_H_I2S1_8CH 76 572#define SRST_H_I2S2_2CH 77 573#define SRST_H_I2S3_2CH 78 574 575/* cru_softrst_con5 */ 576#define SRST_M_I2S0_8CH_TX 80 577#define SRST_M_I2S0_8CH_RX 81 578#define SRST_M_I2S1_8CH_TX 82 579#define SRST_M_I2S1_8CH_RX 83 580#define SRST_M_I2S2_2CH 84 581#define SRST_M_I2S3_2CH_TX 85 582#define SRST_M_I2S3_2CH_RX 86 583#define SRST_H_PDM 87 584#define SRST_M_PDM 88 585#define SRST_H_VAD 89 586#define SRST_H_SPDIF_8CH 90 587#define SRST_M_SPDIF_8CH 91 588#define SRST_H_AUDPWM 92 589#define SRST_S_AUDPWM 93 590#define SRST_H_ACDCDIG 94 591#define SRST_ACDCDIG 95 592 593/* cru_softrst_con6 */ 594#define SRST_A_SECURE_FLASH_NIU 96 595#define SRST_H_SECURE_FLASH_NIU 97 596#define SRST_A_CRYPTO_NS 103 597#define SRST_H_CRYPTO_NS 104 598#define SRST_CRYPTO_NS_CORE 105 599#define SRST_CRYPTO_NS_PKA 106 600#define SRST_CRYPTO_NS_RNG 107 601#define SRST_H_TRNG_NS 108 602#define SRST_TRNG_NS 109 603 604/* cru_softrst_con7 */ 605#define SRST_H_NANDC 112 606#define SRST_N_NANDC 113 607#define SRST_H_SFC 114 608#define SRST_H_SFC_XIP 115 609#define SRST_S_SFC 116 610#define SRST_A_EMMC 117 611#define SRST_H_EMMC 118 612#define SRST_B_EMMC 119 613#define SRST_C_EMMC 120 614#define SRST_T_EMMC 121 615 616/* cru_softrst_con8 */ 617#define SRST_A_PIPE_NIU 128 618#define SRST_P_PIPE_NIU 130 619#define SRST_P_PIPE_GRF 133 620#define SRST_A_SATA0 134 621#define SRST_SATA0_PIPE 135 622#define SRST_SATA0_PMALIVE 136 623#define SRST_SATA0_RXOOB 137 624#define SRST_A_SATA1 138 625#define SRST_SATA1_PIPE 139 626#define SRST_SATA1_PMALIVE 140 627#define SRST_SATA1_RXOOB 141 628 629/* cru_softrst_con9 */ 630#define SRST_A_SATA2 144 631#define SRST_SATA2_PIPE 145 632#define SRST_SATA2_PMALIVE 146 633#define SRST_SATA2_RXOOB 147 634#define SRST_USB3OTG0 148 635#define SRST_USB3OTG1 149 636#define SRST_XPCS 150 637#define SRST_XPCS_TX_DIV10 151 638#define SRST_XPCS_RX_DIV10 152 639#define SRST_XPCS_XGXS_RX 153 640 641/* cru_softrst_con10 */ 642#define SRST_P_PCIE20 160 643#define SRST_PCIE20_POWERUP 161 644#define SRST_MSTR_ARESET_PCIE20 162 645#define SRST_SLV_ARESET_PCIE20 163 646#define SRST_DBI_ARESET_PCIE20 164 647#define SRST_BRESET_PCIE20 165 648#define SRST_PERST_PCIE20 166 649#define SRST_CORE_RST_PCIE20 167 650#define SRST_NSTICKY_RST_PCIE20 168 651#define SRST_STICKY_RST_PCIE20 169 652#define SRST_PWR_RST_PCIE20 170 653 654/* cru_softrst_con11 */ 655#define SRST_P_PCIE30X1 176 656#define SRST_PCIE30X1_POWERUP 177 657#define SRST_M_ARESET_PCIE30X1 178 658#define SRST_S_ARESET_PCIE30X1 179 659#define SRST_D_ARESET_PCIE30X1 180 660#define SRST_BRESET_PCIE30X1 181 661#define SRST_PERST_PCIE30X1 182 662#define SRST_CORE_RST_PCIE30X1 183 663#define SRST_NSTC_RST_PCIE30X1 184 664#define SRST_STC_RST_PCIE30X1 185 665#define SRST_PWR_RST_PCIE30X1 186 666 667/* cru_softrst_con12 */ 668#define SRST_P_PCIE30X2 192 669#define SRST_PCIE30X2_POWERUP 193 670#define SRST_M_ARESET_PCIE30X2 194 671#define SRST_S_ARESET_PCIE30X2 195 672#define SRST_D_ARESET_PCIE30X2 196 673#define SRST_BRESET_PCIE30X2 197 674#define SRST_PERST_PCIE30X2 198 675#define SRST_CORE_RST_PCIE30X2 199 676#define SRST_NSTC_RST_PCIE30X2 200 677#define SRST_STC_RST_PCIE30X2 201 678#define SRST_PWR_RST_PCIE30X2 202 679 680/* cru_softrst_con13 */ 681#define SRST_A_PHP_NIU 208 682#define SRST_H_PHP_NIU 209 683#define SRST_P_PHP_NIU 210 684#define SRST_H_SDMMC0 211 685#define SRST_SDMMC0 212 686#define SRST_H_SDMMC1 213 687#define SRST_SDMMC1 214 688#define SRST_A_GMAC0 215 689#define SRST_GMAC0_TIMESTAMP 216 690 691/* cru_softrst_con14 */ 692#define SRST_A_USB_NIU 224 693#define SRST_H_USB_NIU 225 694#define SRST_P_USB_NIU 226 695#define SRST_P_USB_GRF 227 696#define SRST_H_USB2HOST0 228 697#define SRST_H_USB2HOST0_ARB 229 698#define SRST_USB2HOST0_UTMI 230 699#define SRST_H_USB2HOST1 231 700#define SRST_H_USB2HOST1_ARB 232 701#define SRST_USB2HOST1_UTMI 233 702#define SRST_H_SDMMC2 234 703#define SRST_SDMMC2 235 704#define SRST_A_GMAC1 236 705#define SRST_GMAC1_TIMESTAMP 237 706 707/* cru_softrst_con15 */ 708#define SRST_A_VI_NIU 240 709#define SRST_H_VI_NIU 241 710#define SRST_P_VI_NIU 242 711#define SRST_A_VICAP 247 712#define SRST_H_VICAP 248 713#define SRST_D_VICAP 249 714#define SRST_I_VICAP 250 715#define SRST_P_VICAP 251 716#define SRST_H_ISP 252 717#define SRST_ISP 253 718#define SRST_P_CSI2HOST1 255 719 720/* cru_softrst_con16 */ 721#define SRST_A_VO_NIU 256 722#define SRST_H_VO_NIU 257 723#define SRST_P_VO_NIU 258 724#define SRST_A_VOP_NIU 259 725#define SRST_A_VOP 260 726#define SRST_H_VOP 261 727#define SRST_VOP0 262 728#define SRST_VOP1 263 729#define SRST_VOP2 264 730#define SRST_VOP_PWM 265 731#define SRST_A_HDCP 266 732#define SRST_H_HDCP 267 733#define SRST_P_HDCP 268 734#define SRST_P_HDMI_HOST 270 735#define SRST_HDMI_HOST 271 736 737/* cru_softrst_con17 */ 738#define SRST_P_DSITX_0 272 739#define SRST_P_DSITX_1 273 740#define SRST_P_EDP_CTRL 274 741#define SRST_EDP_24M 275 742#define SRST_A_VPU_NIU 280 743#define SRST_H_VPU_NIU 281 744#define SRST_A_VPU 282 745#define SRST_H_VPU 283 746#define SRST_H_EINK 286 747#define SRST_P_EINK 287 748 749/* cru_softrst_con18 */ 750#define SRST_A_RGA_NIU 288 751#define SRST_H_RGA_NIU 289 752#define SRST_P_RGA_NIU 290 753#define SRST_A_RGA 292 754#define SRST_H_RGA 293 755#define SRST_RGA_CORE 294 756#define SRST_A_IEP 295 757#define SRST_H_IEP 296 758#define SRST_IEP_CORE 297 759#define SRST_H_EBC 298 760#define SRST_D_EBC 299 761#define SRST_A_JDEC 300 762#define SRST_H_JDEC 301 763#define SRST_A_JENC 302 764#define SRST_H_JENC 303 765 766/* cru_softrst_con19 */ 767#define SRST_A_VENC_NIU 304 768#define SRST_H_VENC_NIU 305 769#define SRST_A_RKVENC 307 770#define SRST_H_RKVENC 308 771#define SRST_RKVENC_CORE 309 772 773/* cru_softrst_con20 */ 774#define SRST_A_RKVDEC_NIU 320 775#define SRST_H_RKVDEC_NIU 321 776#define SRST_A_RKVDEC 322 777#define SRST_H_RKVDEC 323 778#define SRST_RKVDEC_CA 324 779#define SRST_RKVDEC_CORE 325 780#define SRST_RKVDEC_HEVC_CA 326 781 782/* cru_softrst_con21 */ 783#define SRST_A_BUS_NIU 336 784#define SRST_P_BUS_NIU 338 785#define SRST_P_CAN0 340 786#define SRST_CAN0 341 787#define SRST_P_CAN1 342 788#define SRST_CAN1 343 789#define SRST_P_CAN2 344 790#define SRST_CAN2 345 791#define SRST_P_GPIO1 346 792#define SRST_GPIO1 347 793#define SRST_P_GPIO2 348 794#define SRST_GPIO2 349 795#define SRST_P_GPIO3 350 796#define SRST_GPIO3 351 797 798/* cru_softrst_con22 */ 799#define SRST_P_GPIO4 352 800#define SRST_GPIO4 353 801#define SRST_P_I2C1 354 802#define SRST_I2C1 355 803#define SRST_P_I2C2 356 804#define SRST_I2C2 357 805#define SRST_P_I2C3 358 806#define SRST_I2C3 359 807#define SRST_P_I2C4 360 808#define SRST_I2C4 361 809#define SRST_P_I2C5 362 810#define SRST_I2C5 363 811#define SRST_P_OTPC_NS 364 812#define SRST_OTPC_NS_SBPI 365 813#define SRST_OTPC_NS_USR 366 814 815/* cru_softrst_con23 */ 816#define SRST_P_PWM1 368 817#define SRST_PWM1 369 818#define SRST_P_PWM2 370 819#define SRST_PWM2 371 820#define SRST_P_PWM3 372 821#define SRST_PWM3 373 822#define SRST_P_SPI0 374 823#define SRST_SPI0 375 824#define SRST_P_SPI1 376 825#define SRST_SPI1 377 826#define SRST_P_SPI2 378 827#define SRST_SPI2 379 828#define SRST_P_SPI3 380 829#define SRST_SPI3 381 830 831/* cru_softrst_con24 */ 832#define SRST_P_SARADC 384 833#define SRST_P_TSADC 385 834#define SRST_TSADC 386 835#define SRST_P_TIMER 387 836#define SRST_TIMER0 388 837#define SRST_TIMER1 389 838#define SRST_TIMER2 390 839#define SRST_TIMER3 391 840#define SRST_TIMER4 392 841#define SRST_TIMER5 393 842#define SRST_P_UART1 394 843#define SRST_S_UART1 395 844 845/* cru_softrst_con25 */ 846#define SRST_P_UART2 400 847#define SRST_S_UART2 401 848#define SRST_P_UART3 402 849#define SRST_S_UART3 403 850#define SRST_P_UART4 404 851#define SRST_S_UART4 405 852#define SRST_P_UART5 406 853#define SRST_S_UART5 407 854#define SRST_P_UART6 408 855#define SRST_S_UART6 409 856#define SRST_P_UART7 410 857#define SRST_S_UART7 411 858#define SRST_P_UART8 412 859#define SRST_S_UART8 413 860#define SRST_P_UART9 414 861#define SRST_S_UART9 415 862 863/* cru_softrst_con26 */ 864#define SRST_P_GRF 416 865#define SRST_P_GRF_VCCIO12 417 866#define SRST_P_GRF_VCCIO34 418 867#define SRST_P_GRF_VCCIO567 419 868#define SRST_P_SCR 420 869#define SRST_P_WDT_NS 421 870#define SRST_T_WDT_NS 422 871#define SRST_P_DFT2APB 423 872#define SRST_A_MCU 426 873#define SRST_P_INTMUX 427 874#define SRST_P_MAILBOX 428 875 876/* cru_softrst_con27 */ 877#define SRST_A_TOP_HIGH_NIU 432 878#define SRST_A_TOP_LOW_NIU 433 879#define SRST_H_TOP_NIU 434 880#define SRST_P_TOP_NIU 435 881#define SRST_P_TOP_CRU 438 882#define SRST_P_DDRPHY 439 883#define SRST_DDRPHY 440 884#define SRST_P_MIPICSIPHY 442 885#define SRST_P_MIPIDSIPHY0 443 886#define SRST_P_MIPIDSIPHY1 444 887#define SRST_P_PCIE30PHY 445 888#define SRST_PCIE30PHY 446 889#define SRST_P_PCIE30PHY_GRF 447 890 891/* cru_softrst_con28 */ 892#define SRST_P_APB2ASB_LEFT 448 893#define SRST_P_APB2ASB_BOTTOM 449 894#define SRST_P_ASB2APB_LEFT 450 895#define SRST_P_ASB2APB_BOTTOM 451 896#define SRST_P_PIPEPHY0 452 897#define SRST_PIPEPHY0 453 898#define SRST_P_PIPEPHY1 454 899#define SRST_PIPEPHY1 455 900#define SRST_P_PIPEPHY2 456 901#define SRST_PIPEPHY2 457 902#define SRST_P_USB2PHY0_GRF 458 903#define SRST_P_USB2PHY1_GRF 459 904#define SRST_P_CPU_BOOST 460 905#define SRST_CPU_BOOST 461 906#define SRST_P_OTPPHY 462 907#define SRST_OTPPHY 463 908 909/* cru_softrst_con29 */ 910#define SRST_USB2PHY0_POR 464 911#define SRST_USB2PHY0_USB3OTG0 465 912#define SRST_USB2PHY0_USB3OTG1 466 913#define SRST_USB2PHY1_POR 467 914#define SRST_USB2PHY1_USB2HOST0 468 915#define SRST_USB2PHY1_USB2HOST1 469 916#define SRST_P_EDPPHY_GRF 470 917#define SRST_TSADCPHY 471 918#define SRST_GMAC0_DELAYLINE 472 919#define SRST_GMAC1_DELAYLINE 473 920#define SRST_OTPC_ARB 474 921#define SRST_P_PIPEPHY0_GRF 475 922#define SRST_P_PIPEPHY1_GRF 476 923#define SRST_P_PIPEPHY2_GRF 477 924 925#endif 926