1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2014, Freescale Semiconductor 4 */ 5 6#ifndef _ASM_ARMV7_LS102XA_CONFIG_ 7#define _ASM_ARMV7_LS102XA_CONFIG_ 8 9#define OCRAM_BASE_ADDR 0x10000000 10#define OCRAM_SIZE 0x00010000 11#define OCRAM_BASE_S_ADDR 0x10010000 12#define OCRAM_S_SIZE 0x00010000 13 14#define CONFIG_SYS_DCSRBAR 0x20000000 15 16#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 17#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) 18 19#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) 20#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 21#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 23#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 24#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 26#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 27#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 28#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 29#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 30#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 31#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 32#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) 33#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 34#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) 35#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) 36#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 37#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 38 39#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 40#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 41#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 42#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 43#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 44#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 45 46#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 47#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 48 49#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) 50 51#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 52#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 53#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 54 55#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 56 57#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 58#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 59 60#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 61 62#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 63#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 64 65#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL 66#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL 67#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL 68#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL 69#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ 70/* 71 * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) 72 * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. 73 */ 74#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ 75 CONFIG_SYS_PCIE1_VIRT_ADDR) 76#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ 77 CONFIG_SYS_PCIE2_VIRT_ADDR) 78 79/* SATA */ 80#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 81#ifdef CONFIG_DDR_SPD 82#define CONFIG_VERY_BIG_RAM 83#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 84#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE 85#endif 86 87#define CONFIG_SYS_FSL_IFC_BE 88#define CONFIG_SYS_FSL_ESDHC_BE 89#define CONFIG_SYS_FSL_WDOG_BE 90#define CONFIG_SYS_FSL_DSPI_BE 91#define CONFIG_SYS_FSL_SEC_MON_LE 92#define CONFIG_SYS_FSL_SFP_VER_3_2 93#define CONFIG_SYS_FSL_SFP_BE 94#define CONFIG_SYS_FSL_SRK_LE 95 96#define DCU_LAYER_MAX_NUM 16 97 98#ifdef CONFIG_ARCH_LS1021A 99#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 100#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 101#else 102#error SoC not defined 103#endif 104 105#define FSL_IFC_COMPAT "fsl,ifc" 106#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" 107#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" 108 109#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ 110