1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4 * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> 5 */ 6 7#ifndef _IMX_REGS_H 8#define _IMX_REGS_H 9 10#include <asm/arch/regs-rtc.h> 11 12#ifndef __ASSEMBLY__ 13 14extern void imx_gpio_mode (int gpio_mode); 15 16#ifdef CONFIG_MXC_UART 17extern void mx27_uart1_init_pins(void); 18#endif /* CONFIG_MXC_UART */ 19 20#ifdef CONFIG_FEC_MXC 21extern void mx27_fec_init_pins(void); 22#endif /* CONFIG_FEC_MXC */ 23 24#ifdef CONFIG_MMC_MXC 25extern void mx27_sd1_init_pins(void); 26extern void mx27_sd2_init_pins(void); 27#endif /* CONFIG_MMC_MXC */ 28 29/* AIPI */ 30struct aipi_regs { 31 u32 psr0; 32 u32 psr1; 33}; 34 35/* System Control */ 36struct system_control_regs { 37 u32 res[5]; 38 u32 fmcr; 39 u32 gpcr; 40 u32 wbcr; 41 u32 dscr1; 42 u32 dscr2; 43 u32 dscr3; 44 u32 dscr4; 45 u32 dscr5; 46 u32 dscr6; 47 u32 dscr7; 48 u32 dscr8; 49 u32 dscr9; 50 u32 dscr10; 51 u32 dscr11; 52 u32 dscr12; 53 u32 dscr13; 54 u32 pscr; 55 u32 pmcr; 56 u32 res1; 57 u32 dcvr0; 58 u32 dcvr1; 59 u32 dcvr2; 60 u32 dcvr3; 61}; 62 63/* Chip Select Registers */ 64struct weim_regs { 65 u32 cs0u; /* Chip Select 0 Upper Register */ 66 u32 cs0l; /* Chip Select 0 Lower Register */ 67 u32 cs0a; /* Chip Select 0 Addition Register */ 68 u32 pad0; 69 u32 cs1u; /* Chip Select 1 Upper Register */ 70 u32 cs1l; /* Chip Select 1 Lower Register */ 71 u32 cs1a; /* Chip Select 1 Addition Register */ 72 u32 pad1; 73 u32 cs2u; /* Chip Select 2 Upper Register */ 74 u32 cs2l; /* Chip Select 2 Lower Register */ 75 u32 cs2a; /* Chip Select 2 Addition Register */ 76 u32 pad2; 77 u32 cs3u; /* Chip Select 3 Upper Register */ 78 u32 cs3l; /* Chip Select 3 Lower Register */ 79 u32 cs3a; /* Chip Select 3 Addition Register */ 80 u32 pad3; 81 u32 cs4u; /* Chip Select 4 Upper Register */ 82 u32 cs4l; /* Chip Select 4 Lower Register */ 83 u32 cs4a; /* Chip Select 4 Addition Register */ 84 u32 pad4; 85 u32 cs5u; /* Chip Select 5 Upper Register */ 86 u32 cs5l; /* Chip Select 5 Lower Register */ 87 u32 cs5a; /* Chip Select 5 Addition Register */ 88 u32 pad5; 89 u32 eim; /* WEIM Configuration Register */ 90}; 91 92/* SDRAM Controller registers */ 93struct esdramc_regs { 94/* Enhanced SDRAM Control Register 0 */ 95 u32 esdctl0; 96/* Enhanced SDRAM Configuration Register 0 */ 97 u32 esdcfg0; 98/* Enhanced SDRAM Control Register 1 */ 99 u32 esdctl1; 100/* Enhanced SDRAM Configuration Register 1 */ 101 u32 esdcfg1; 102/* Enhanced SDRAM Miscellanious Register */ 103 u32 esdmisc; 104}; 105 106/* Watchdog Registers*/ 107struct wdog_regs { 108 u16 wcr; 109 u16 wsr; 110 u16 wstr; 111}; 112 113/* PLL registers */ 114struct pll_regs { 115 u32 cscr; /* Clock Source Control Register */ 116 u32 mpctl0; /* MCU PLL Control Register 0 */ 117 u32 mpctl1; /* MCU PLL Control Register 1 */ 118 u32 spctl0; /* System PLL Control Register 0 */ 119 u32 spctl1; /* System PLL Control Register 1 */ 120 u32 osc26mctl; /* Oscillator 26M Register */ 121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */ 122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */ 123 u32 pccr0; /* Peripheral Clock Control Register 0 */ 124 u32 pccr1; /* Peripheral Clock Control Register 1 */ 125 u32 ccsr; /* Clock Control Status Register */ 126}; 127 128/* 129 * Definitions for the clocksource registers 130 */ 131struct gpt_regs { 132 u32 gpt_tctl; 133 u32 gpt_tprer; 134 u32 gpt_tcmp; 135 u32 gpt_tcr; 136 u32 gpt_tcn; 137 u32 gpt_tstat; 138}; 139 140/* IIM Control Registers */ 141struct iim_regs { 142 u32 iim_stat; 143 u32 iim_statm; 144 u32 iim_err; 145 u32 iim_emask; 146 u32 iim_fctl; 147 u32 iim_ua; 148 u32 iim_la; 149 u32 iim_sdat; 150 u32 iim_prev; 151 u32 iim_srev; 152 u32 iim_prg_p; 153 u32 iim_scs0; 154 u32 iim_scs1; 155 u32 iim_scs2; 156 u32 iim_scs3; 157 u32 res[0x1f1]; 158 struct fuse_bank { 159 u32 fuse_regs[0x20]; 160 u32 fuse_rsvd[0xe0]; 161 } bank[2]; 162}; 163 164struct fuse_bank0_regs { 165 u32 fuse0_3[5]; 166 u32 mac_addr[6]; 167 u32 fuse10_31[0x16]; 168}; 169 170#endif 171 172#define ARCH_MXC 173 174#define IMX_IO_BASE 0x10000000 175 176#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) 177#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) 178#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) 179#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) 180#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) 181#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) 182#define UART1_BASE_ADDR (0x0a000 + IMX_IO_BASE) 183#define UART2_BASE_ADDR (0x0b000 + IMX_IO_BASE) 184#define UART3_BASE_ADDR (0x0c000 + IMX_IO_BASE) 185#define UART4_BASE_ADDR (0x0d000 + IMX_IO_BASE) 186#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) 187#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) 188#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) 189#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) 190#define UART5_BASE_ADDR (0x1b000 + IMX_IO_BASE) 191#define UART6_BASE_ADDR (0x1c000 + IMX_IO_BASE) 192#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) 193#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) 194#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) 195#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) 196#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) 197#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) 198#define IIM_BASE_ADDR IMX_IIM_BASE 199#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) 200 201#define IMX_NFC_BASE (0xD8000000) 202#define IMX_ESD_BASE (0xD8001000) 203#define IMX_WEIM_BASE (0xD8002000) 204 205#define NFC_BASE_ADDR IMX_NFC_BASE 206 207#define UART_BASE_ADDR(n) ( \ 208 !!sizeof(struct { \ 209 static_assert((n) >= 1 && (n) <= 6); \ 210 int pad; \ 211 }) * ( \ 212 (n) == 1 ? UART1_BASE_ADDR : \ 213 (n) == 2 ? UART2_BASE_ADDR : \ 214 (n) == 3 ? UART3_BASE_ADDR : \ 215 (n) == 4 ? UART4_BASE_ADDR : \ 216 (n) == 5 ? UART5_BASE_ADDR : \ 217 UART6_BASE_ADDR) \ 218 ) 219 220/* FMCR System Control bit definition*/ 221#define UART4_RXD_CTL (1 << 25) 222#define UART4_RTS_CTL (1 << 24) 223#define KP_COL6_CTL (1 << 18) 224#define KP_ROW7_CTL (1 << 17) 225#define KP_ROW6_CTL (1 << 16) 226#define PC_WAIT_B_CTL (1 << 14) 227#define PC_READY_CTL (1 << 13) 228#define PC_VS1_CTL (1 << 12) 229#define PC_VS2_CTL (1 << 11) 230#define PC_BVD1_CTL (1 << 10) 231#define PC_BVD2_CTL (1 << 9) 232#define IOS16_CTL (1 << 8) 233#define NF_FMS (1 << 5) 234#define NF_16BIT_SEL (1 << 4) 235#define SLCDC_SEL (1 << 2) 236#define SDCS1_SEL (1 << 1) 237#define SDCS0_SEL (1 << 0) 238 239 240/* important definition of some bits of WCR */ 241#define WCR_WDE 0x04 242 243#define CSCR_MPEN (1 << 0) 244#define CSCR_SPEN (1 << 1) 245#define CSCR_FPM_EN (1 << 2) 246#define CSCR_OSC26M_DIS (1 << 3) 247#define CSCR_OSC26M_DIV1P5 (1 << 4) 248#define CSCR_AHB_DIV 249#define CSCR_ARM_DIV 250#define CSCR_ARM_SRC_MPLL (1 << 15) 251#define CSCR_MCU_SEL (1 << 16) 252#define CSCR_SP_SEL (1 << 17) 253#define CSCR_MPLL_RESTART (1 << 18) 254#define CSCR_SPLL_RESTART (1 << 19) 255#define CSCR_MSHC_SEL (1 << 20) 256#define CSCR_H264_SEL (1 << 21) 257#define CSCR_SSI1_SEL (1 << 22) 258#define CSCR_SSI2_SEL (1 << 23) 259#define CSCR_SD_CNT 260#define CSCR_USB_DIV 261#define CSCR_UPDATE_DIS (1 << 31) 262 263#define MPCTL1_BRMO (1 << 6) 264#define MPCTL1_LF (1 << 15) 265 266#define PCCR0_SSI2_EN (1 << 0) 267#define PCCR0_SSI1_EN (1 << 1) 268#define PCCR0_SLCDC_EN (1 << 2) 269#define PCCR0_SDHC3_EN (1 << 3) 270#define PCCR0_SDHC2_EN (1 << 4) 271#define PCCR0_SDHC1_EN (1 << 5) 272#define PCCR0_SDC_EN (1 << 6) 273#define PCCR0_SAHARA_EN (1 << 7) 274#define PCCR0_RTIC_EN (1 << 8) 275#define PCCR0_RTC_EN (1 << 9) 276#define PCCR0_PWM_EN (1 << 11) 277#define PCCR0_OWIRE_EN (1 << 12) 278#define PCCR0_MSHC_EN (1 << 13) 279#define PCCR0_LCDC_EN (1 << 14) 280#define PCCR0_KPP_EN (1 << 15) 281#define PCCR0_IIM_EN (1 << 16) 282#define PCCR0_I2C2_EN (1 << 17) 283#define PCCR0_I2C1_EN (1 << 18) 284#define PCCR0_GPT6_EN (1 << 19) 285#define PCCR0_GPT5_EN (1 << 20) 286#define PCCR0_GPT4_EN (1 << 21) 287#define PCCR0_GPT3_EN (1 << 22) 288#define PCCR0_GPT2_EN (1 << 23) 289#define PCCR0_GPT1_EN (1 << 24) 290#define PCCR0_GPIO_EN (1 << 25) 291#define PCCR0_FEC_EN (1 << 26) 292#define PCCR0_EMMA_EN (1 << 27) 293#define PCCR0_DMA_EN (1 << 28) 294#define PCCR0_CSPI3_EN (1 << 29) 295#define PCCR0_CSPI2_EN (1 << 30) 296#define PCCR0_CSPI1_EN (1 << 31) 297 298#define PCCR1_MSHC_BAUDEN (1 << 2) 299#define PCCR1_NFC_BAUDEN (1 << 3) 300#define PCCR1_SSI2_BAUDEN (1 << 4) 301#define PCCR1_SSI1_BAUDEN (1 << 5) 302#define PCCR1_H264_BAUDEN (1 << 6) 303#define PCCR1_PERCLK4_EN (1 << 7) 304#define PCCR1_PERCLK3_EN (1 << 8) 305#define PCCR1_PERCLK2_EN (1 << 9) 306#define PCCR1_PERCLK1_EN (1 << 10) 307#define PCCR1_HCLK_USB (1 << 11) 308#define PCCR1_HCLK_SLCDC (1 << 12) 309#define PCCR1_HCLK_SAHARA (1 << 13) 310#define PCCR1_HCLK_RTIC (1 << 14) 311#define PCCR1_HCLK_LCDC (1 << 15) 312#define PCCR1_HCLK_H264 (1 << 16) 313#define PCCR1_HCLK_FEC (1 << 17) 314#define PCCR1_HCLK_EMMA (1 << 18) 315#define PCCR1_HCLK_EMI (1 << 19) 316#define PCCR1_HCLK_DMA (1 << 20) 317#define PCCR1_HCLK_CSI (1 << 21) 318#define PCCR1_HCLK_BROM (1 << 22) 319#define PCCR1_HCLK_ATA (1 << 23) 320#define PCCR1_WDT_EN (1 << 24) 321#define PCCR1_USB_EN (1 << 25) 322#define PCCR1_UART6_EN (1 << 26) 323#define PCCR1_UART5_EN (1 << 27) 324#define PCCR1_UART4_EN (1 << 28) 325#define PCCR1_UART3_EN (1 << 29) 326#define PCCR1_UART2_EN (1 << 30) 327#define PCCR1_UART1_EN (1 << 31) 328 329/* SDRAM Controller registers bitfields */ 330#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) 331#define ESDCTL_BL (1 << 7) 332#define ESDCTL_FP (1 << 8) 333#define ESDCTL_PWDT(x) (((x) & 3) << 10) 334#define ESDCTL_SREFR(x) (((x) & 7) << 13) 335#define ESDCTL_DSIZ_16_UPPER (0 << 16) 336#define ESDCTL_DSIZ_16_LOWER (1 << 16) 337#define ESDCTL_DSIZ_32 (2 << 16) 338#define ESDCTL_COL8 (0 << 20) 339#define ESDCTL_COL9 (1 << 20) 340#define ESDCTL_COL10 (2 << 20) 341#define ESDCTL_ROW11 (0 << 24) 342#define ESDCTL_ROW12 (1 << 24) 343#define ESDCTL_ROW13 (2 << 24) 344#define ESDCTL_ROW14 (3 << 24) 345#define ESDCTL_ROW15 (4 << 24) 346#define ESDCTL_SP (1 << 27) 347#define ESDCTL_SMODE_NORMAL (0 << 28) 348#define ESDCTL_SMODE_PRECHARGE (1 << 28) 349#define ESDCTL_SMODE_AUTO_REF (2 << 28) 350#define ESDCTL_SMODE_LOAD_MODE (3 << 28) 351#define ESDCTL_SMODE_MAN_REF (4 << 28) 352#define ESDCTL_SDE (1 << 31) 353 354#define ESDCFG_TRC(x) (((x) & 0xf) << 0) 355#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) 356#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) 357#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) 358#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) 359#define ESDCFG_TWR (1 << 15) 360#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) 361#define ESDCFG_TRP(x) (((x) & 0x3) << 18) 362#define ESDCFG_TWTR (1 << 20) 363#define ESDCFG_TXP(x) (((x) & 0x3) << 21) 364 365#define ESDMISC_RST (1 << 1) 366#define ESDMISC_MDDREN (1 << 2) 367#define ESDMISC_MDDR_DL_RST (1 << 3) 368#define ESDMISC_MDDR_MDIS (1 << 4) 369#define ESDMISC_LHD (1 << 5) 370#define ESDMISC_MA10_SHARE (1 << 6) 371#define ESDMISC_SDRAM_RDY (1 << 31) 372 373#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) 374#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) 375#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) 376#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) 377#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) 378#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) 379#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) 380#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) 381#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) 382 383#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) 384#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) 385#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) 386#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) 387#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) 388#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) 389#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) 390#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) 391#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) 392#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) 393#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) 394#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) 395#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) 396#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) 397#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) 398#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) 399#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) 400#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) 401 402#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) 403#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) 404#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) 405#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) 406#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) 407#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) 408#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) 409#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) 410#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) 411#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) 412#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) 413#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) 414#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) 415#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) 416#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) 417#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) 418#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) 419#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) 420#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) 421#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) 422#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) 423#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) 424#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) 425#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) 426#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) 427#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) 428#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) 429#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) 430#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) 431#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) 432#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) 433 434/* Clocksource Bitfields */ 435#define TCTL_SWR (1 << 15) /* Software reset */ 436#define TCTL_FRR (1 << 8) /* Freerun / restart */ 437#define TCTL_CAP (3 << 6) /* Capture Edge */ 438#define TCTL_OM (1 << 5) /* output mode */ 439#define TCTL_IRQEN (1 << 4) /* interrupt enable */ 440#define TCTL_CLKSOURCE 1 /* Clock source bit position */ 441#define TCTL_TEN 1 /* Timer enable */ 442#define TPRER_PRES 0xff /* Prescale */ 443#define TSTAT_CAPT (1 << 1) /* Capture event */ 444#define TSTAT_COMP 1 /* Compare event */ 445 446#define GPIO1_BASE_ADDR 0x10015000 447#define GPIO2_BASE_ADDR 0x10015100 448#define GPIO3_BASE_ADDR 0x10015200 449#define GPIO4_BASE_ADDR 0x10015300 450#define GPIO5_BASE_ADDR 0x10015400 451#define GPIO6_BASE_ADDR 0x10015500 452 453#define GPIO_OUT (1 << 8) 454#define GPIO_IN (0 << 8) 455#define GPIO_PUEN (1 << 9) 456 457#define GPIO_PF (1 << 10) 458#define GPIO_AF (1 << 11) 459 460#define GPIO_OCR_SHIFT 12 461#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) 462#define GPIO_AIN (0 << GPIO_OCR_SHIFT) 463#define GPIO_BIN (1 << GPIO_OCR_SHIFT) 464#define GPIO_CIN (2 << GPIO_OCR_SHIFT) 465#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) 466 467#define GPIO_AOUT_SHIFT 14 468#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) 469#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) 470#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) 471#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) 472#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) 473 474#define GPIO_BOUT_SHIFT 16 475#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) 476#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) 477#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) 478#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) 479#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) 480 481#define IIM_STAT_BUSY (1 << 7) 482#define IIM_STAT_PRGD (1 << 1) 483#define IIM_STAT_SNSD (1 << 0) 484#define IIM_ERR_PRGE (1 << 7) 485#define IIM_ERR_WPE (1 << 6) 486#define IIM_ERR_OPE (1 << 5) 487#define IIM_ERR_RPE (1 << 4) 488#define IIM_ERR_WLRE (1 << 3) 489#define IIM_ERR_SNSE (1 << 2) 490#define IIM_ERR_PARITYE (1 << 1) 491 492#endif /* _IMX_REGS_H */ 493