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9#ifndef _SUNXI_DRAM_SUN50I_H6_H
10#define _SUNXI_DRAM_SUN50I_H6_H
11
12#include <stdbool.h>
13#ifndef __ASSEMBLY__
14#include <linux/bitops.h>
15#endif
16
17enum sunxi_dram_type {
18 SUNXI_DRAM_TYPE_DDR3 = 3,
19 SUNXI_DRAM_TYPE_DDR4,
20 SUNXI_DRAM_TYPE_LPDDR2 = 6,
21 SUNXI_DRAM_TYPE_LPDDR3,
22};
23
24static inline bool sunxi_dram_is_lpddr(int type)
25{
26 return type >= SUNXI_DRAM_TYPE_LPDDR2;
27}
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32
33struct sunxi_mctl_com_reg {
34 u32 cr;
35 u8 reserved_0x004[4];
36 u32 unk_0x008;
37 u32 tmr;
38 u8 reserved_0x010[4];
39 u32 unk_0x014;
40 u8 reserved_0x018[8];
41 u32 maer0;
42 u32 maer1;
43 u32 maer2;
44 u8 reserved_0x02c[468];
45 u32 bwcr;
46 u8 reserved_0x204[12];
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51 struct {
52 u32 cfg0;
53 u32 cfg1;
54 u8 reserved_0x8[8];
55 } master[41];
56};
57check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
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75struct sunxi_mctl_ctl_reg {
76 u32 mstr;
77 u32 statr;
78 u32 mstr1;
79 u32 unk_0x00c;
80 u32 mrctrl0;
81 u32 mrctrl1;
82 u32 mrstatr;
83 u32 mrctrl2;
84 u32 derateen;
85 u32 derateint;
86 u8 reserved_0x028[8];
87 u32 pwrctl;
88 u32 pwrtmg;
89 u32 hwlpctl;
90 u8 reserved_0x03c[20];
91 u32 rfshctl0;
92 u32 rfshctl1;
93 u8 reserved_0x058[8];
94 u32 rfshctl3;
95 u32 rfshtmg;
96 u8 reserved_0x068[104];
97 u32 init[8];
98 u32 dimmctl;
99 u32 rankctl;
100 u8 reserved_0x0f8[8];
101 u32 dramtmg[17];
102 u8 reserved_0x144[60];
103 u32 zqctl[3];
104 u32 zqstat;
105 u32 dfitmg0;
106 u32 dfitmg1;
107 u32 dfilpcfg[2];
108 u32 dfiupd[3];
109 u32 reserved_0x1ac;
110 u32 dfimisc;
111 u32 dfitmg2;
112 u8 reserved_0x1b8[8];
113 u32 dbictl;
114 u8 reserved_0x1c4[60];
115 u32 addrmap[12];
116 u8 reserved_0x230[16];
117 u32 odtcfg;
118 u32 odtmap;
119 u8 reserved_0x248[8];
120 u32 sched[2];
121 u8 reserved_0x258[180];
122 u32 dbgcmd;
123 u32 dbgstat;
124 u8 reserved_0x314[12];
125 u32 swctl;
126 u32 swstat;
127};
128check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
129
130#define MSTR_DEVICETYPE_DDR3 BIT(0)
131#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
132#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
133#define MSTR_DEVICETYPE_DDR4 BIT(4)
134#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
135#define MSTR_2TMODE BIT(10)
136#define MSTR_BUSWIDTH_FULL (0 << 12)
137#define MSTR_BUSWIDTH_HALF (1 << 12)
138#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
139#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
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150struct sunxi_mctl_phy_reg {
151 u32 ver;
152 u32 pir;
153 u8 reserved_0x008[8];
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158 u32 pgcr[8];
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163 u8 reserved_0x030[4];
164 u32 pgsr[3];
165 u32 ptr[7];
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173 u8 reserved_0x05c[36];
174 u32 unk_0x080;
175 u8 reserved_0x084[4];
176 u32 dxccr;
177 u8 reserved_0x08c[4];
178 u32 dsgcr;
179 u8 reserved_0x094[4];
180 u32 odtcr;
181 u8 reserved_0x09c[4];
182 u32 aacr;
183 u8 reserved_0x0a4[32];
184 u32 gpr1;
185 u8 reserved_0x0c8[56];
186 u32 dcr;
187 u8 reserved_0x104[12];
188 u32 dtpr[7];
189 u8 reserved_0x12c[20];
190 u32 rdimmgcr[3];
191 u8 reserved_0x14c[4];
192 u32 rdimmcr[5];
193 u8 reserved_0x164[4];
194 u32 schcr[2];
195 u8 reserved_0x170[16];
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199 u32 mr[23];
200 u8 reserved_0x1dc[36];
201 u32 dtcr[2];
202 u32 dtar[3];
203 u8 reserved_0x214[4];
204 u32 dtdr[2];
205 u8 reserved_0x220[16];
206 u32 dtedr0;
207 u32 dtedr1;
208 u32 dtedr2;
209 u32 vtdr;
210 u32 catr[2];
211 u8 reserved_0x248[8];
212 u32 dqsdr[3];
213 u32 dtedr3;
214 u8 reserved_0x260[160];
215 u32 dcuar;
216 u32 dcudr;
217 u32 dcurr;
218 u32 dculr;
219 u32 dcugcr;
220 u32 dcutpr;
221 u32 dcusr[2];
222 u8 reserved_0x320[444];
223 u32 rankidr;
224 u32 riocr[6];
225 u8 reserved_0x4f8[8];
226 u32 aciocr[6];
227 u8 reserved_0x518[8];
228 u32 iovcr[2];
229 u32 vtcr[2];
230 u8 reserved_0x530[16];
231 u32 acbdlr[17];
232 u32 aclcdlr;
233 u8 reserved_0x588[24];
234 u32 acmdlr[2];
235 u8 reserved_0x5a8[216];
236 struct {
237 u32 zqcr;
238 u32 zqpr[2];
239 u32 zqdr[2];
240 u32 zqor[2];
241 u32 zqsr;
242 } zq[2];
243 u8 reserved_0x6c0[64];
244 struct {
245 u32 gcr[7];
246 u8 reserved_0x1c[36];
247 u32 bdlr0;
248 u32 bdlr1;
249 u32 bdlr2;
250 u8 reserved_0x4c[4];
251 u32 bdlr3;
252 u32 bdlr4;
253 u32 bdlr5;
254 u8 reserved_0x5c[4];
255 u32 bdlr6;
256 u8 reserved_0x64[28];
257 u32 lcdlr[6];
258 u8 reserved_0x98[8];
259 u32 mdlr[2];
260 u8 reserved_0xa8[24];
261 u32 gtr0;
262 u8 reserved_0xc4[12];
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267 u32 rsr[4];
268 u32 gsr[4];
269 u8 reserved_0xf0[16];
270 } dx[4];
271};
272check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
273
274#define PIR_INIT BIT(0)
275#define PIR_ZCAL BIT(1)
276#define PIR_CA BIT(2)
277#define PIR_PLLINIT BIT(4)
278#define PIR_DCAL BIT(5)
279#define PIR_PHYRST BIT(6)
280#define PIR_DRAMRST BIT(7)
281#define PIR_DRAMINIT BIT(8)
282#define PIR_WL BIT(9)
283#define PIR_QSGATE BIT(10)
284#define PIR_WLADJ BIT(11)
285#define PIR_RDDSKW BIT(12)
286#define PIR_WRDSKW BIT(13)
287#define PIR_RDEYE BIT(14)
288#define PIR_WREYE BIT(15)
289#define PIR_VREF BIT(17)
290#define PIR_CTLDINIT BIT(18)
291#define PIR_DQS2DQ BIT(20)
292#define PIR_DCALPSE BIT(29)
293#define PIR_ZCALBYP BIT(30)
294
295#define DCR_LPDDR3 (1 << 0)
296#define DCR_DDR3 (3 << 0)
297#define DCR_DDR4 (4 << 0)
298#define DCR_DDR8BANK BIT(3)
299#define DCR_DDR2T BIT(28)
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307#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
308
309#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
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314#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
315struct dram_para {
316 u32 clk;
317 enum sunxi_dram_type type;
318 u8 cols;
319 u8 rows;
320 u8 ranks;
321 u8 bus_full_width;
322 const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
323 const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
324};
325
326
327static inline int ns_to_t(int nanoseconds)
328{
329 const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
330
331 return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
332}
333
334void mctl_set_timing_params(struct dram_para *para);
335
336#endif
337