LXR uboot/arch/arm/mach-imx/mx7/ddr.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * DDR controller configuration for the i.MX7 architecture
   4 *
   5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
   6 *
   7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
   8 */
   9
  10#include <linux/types.h>
  11#include <asm/io.h>
  12#include <asm/arch/imx-regs.h>
  13#include <asm/arch/crm_regs.h>
  14#include <asm/arch/mx7-ddr.h>
  15#include <common.h>
  16#include <linux/delay.h>
  17
  18/*
  19 * Routine: mx7_dram_cfg
  20 * Description: DDR controller configuration
  21 *
  22 * @ddrc_regs_val: DDRC registers value
  23 * @ddrc_mp_val: DDRC_MP registers value
  24 * @ddr_phy_regs_val: DDR_PHY registers value
  25 * @calib_param: calibration parameters
  26 *
  27 */
  28void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
  29                  struct ddr_phy *ddr_phy_regs_val,
  30                  struct mx7_calibration *calib_param)
  31{
  32        struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
  33        struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
  34        struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
  35        struct ddr_phy *const ddr_phy_regs =
  36                (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
  37        struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
  38                (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  39        int i;
  40
  41        /*
  42         * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
  43         * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
  44         * aresetn_n = 0, presetn = 0. That means reset everything.
  45         */
  46        writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
  47               &src_regs->ddrc_rcr);
  48
  49        /*
  50         * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
  51         * If we assume this is 30 cycles at 100 MHz (about the rate of a
  52         * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
  53         */
  54        udelay(10);
  55
  56        /* De-assert DDR Controller 'preset' and DDR PHY reset */
  57        clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
  58
  59        /* DDR controller configuration */
  60        writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
  61        writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
  62        writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
  63        writel(ddrc_regs_val->init1, &ddrc_regs->init1);
  64        writel(ddrc_regs_val->init0, &ddrc_regs->init0);
  65        writel(ddrc_regs_val->init3, &ddrc_regs->init3);
  66        writel(ddrc_regs_val->init4, &ddrc_regs->init4);
  67        writel(ddrc_regs_val->init5, &ddrc_regs->init5);
  68        writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
  69        writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
  70        writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
  71        writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
  72        writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
  73        writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
  74        writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
  75        writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
  76        writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
  77        writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);
  78        writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
  79        writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
  80        writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
  81        writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
  82        writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
  83        writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
  84        writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
  85        writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
  86        writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
  87        writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
  88        writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
  89        writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
  90
  91        /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
  92        clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
  93
  94        /* PHY configuration */
  95        writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
  96        writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
  97        writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
  98        writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
  99        writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
 100        writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
 101        writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
 102        writel(ddr_phy_regs_val->cmd_sdll_con0 |
 103               DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
 104               &ddr_phy_regs->cmd_sdll_con0);
 105        writel(ddr_phy_regs_val->cmd_sdll_con0 &
 106               ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
 107               &ddr_phy_regs->cmd_sdll_con0);
 108        writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
 109        writel(ddr_phy_regs_val->cmd_deskew_con0,
 110               &ddr_phy_regs->cmd_deskew_con0);
 111        writel(ddr_phy_regs_val->cmd_deskew_con1,
 112               &ddr_phy_regs->cmd_deskew_con1);
 113        writel(ddr_phy_regs_val->cmd_deskew_con2,
 114               &ddr_phy_regs->cmd_deskew_con2);
 115        writel(ddr_phy_regs_val->cmd_deskew_con3,
 116               &ddr_phy_regs->cmd_deskew_con3);
 117        writel(ddr_phy_regs_val->cmd_lvl_con0, &ddr_phy_regs->cmd_lvl_con0);
 118
 119        /* calibration */
 120        for (i = 0; i < calib_param->num_val; i++)
 121                writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
 122
 123        /* Wake_up DDR PHY */
 124        HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
 125        writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
 126               IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
 127               &iomuxc_gpr_regs->gpr[8]);
 128        HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
 129}
 130
 131/*
 132 * Routine: imx_ddr_size
 133 * Description: extract the current DRAM size from the DDRC registers
 134 *
 135 * @return: DRAM size
 136 */
 137unsigned int imx_ddr_size(void)
 138{
 139        struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
 140        u32 reg_val, field_val;
 141        int bits = 0;/* Number of address bits */
 142
 143        /* Count data bus width bits */
 144        reg_val = readl(&ddrc_regs->mstr);
 145        field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
 146        bits += 2 - field_val;
 147        /* Count rank address bits */
 148        field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
 149        if (field_val > 1)
 150                bits += field_val - 1;
 151        /* Count column address bits */
 152        bits += 2;/* Column address 0 and 1 are fixed mapped */
 153        reg_val = readl(&ddrc_regs->addrmap2);
 154        field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
 155        if (field_val <= 7)
 156                bits++;
 157        field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
 158        if (field_val <= 7)
 159                bits++;
 160        field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
 161        if (field_val <= 7)
 162                bits++;
 163        field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
 164        if (field_val <= 7)
 165                bits++;
 166        reg_val = readl(&ddrc_regs->addrmap3);
 167        field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
 168        if (field_val <= 7)
 169                bits++;
 170        field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
 171        if (field_val <= 7)
 172                bits++;
 173        field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
 174        if (field_val <= 7)
 175                bits++;
 176        field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
 177        if (field_val <= 7)
 178                bits++;
 179        reg_val = readl(&ddrc_regs->addrmap4);
 180        field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
 181        if (field_val <= 7)
 182                bits++;
 183        field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
 184        if (field_val <= 7)
 185                bits++;
 186        /* Count row address bits */
 187        reg_val = readl(&ddrc_regs->addrmap5);
 188        field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
 189        if (field_val <= 11)
 190                bits++;
 191        field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
 192        if (field_val <= 11)
 193                bits++;
 194        field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
 195        if (field_val <= 11)
 196                bits += 9;
 197        field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
 198        if (field_val <= 11)
 199                bits++;
 200        reg_val = readl(&ddrc_regs->addrmap6);
 201        field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
 202        if (field_val <= 11)
 203                bits++;
 204        field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
 205        if (field_val <= 11)
 206                bits++;
 207        field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
 208        if (field_val <= 11)
 209                bits++;
 210        field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
 211        if (field_val <= 11)
 212                bits++;
 213        /* Count bank bits */
 214        reg_val = readl(&ddrc_regs->addrmap1);
 215        field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
 216        if (field_val <= 30)
 217                bits++;
 218        field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
 219        if (field_val <= 30)
 220                bits++;
 221        field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
 222        if (field_val <= 29)
 223                bits++;
 224
 225        /* cap to max 2 GB */
 226        if (bits > 31)
 227                bits = 31;
 228
 229        return 1 << bits;
 230}
 231