LXR uboot/arch/arm/mach-s5pc1xx/include/mach/periph.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2012 Samsung Electronics
   4 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
   5 */
   6
   7#ifndef __ASM_ARM_ARCH_PERIPH_H
   8#define __ASM_ARM_ARCH_PERIPH_H
   9
  10/*
  11 * Peripherals required for pinmux configuration. List will
  12 * grow with support for more devices getting added.
  13 * Numbering based on interrupt table.
  14 *
  15 */
  16enum periph_id {
  17        PERIPH_ID_UART0 = 51,
  18        PERIPH_ID_UART1,
  19        PERIPH_ID_UART2,
  20        PERIPH_ID_UART3,
  21        PERIPH_ID_I2C0 = 56,
  22        PERIPH_ID_I2C1,
  23        PERIPH_ID_I2C2,
  24        PERIPH_ID_I2C3,
  25        PERIPH_ID_I2C4,
  26        PERIPH_ID_I2C5,
  27        PERIPH_ID_I2C6,
  28        PERIPH_ID_I2C7,
  29        PERIPH_ID_SPI0 = 68,
  30        PERIPH_ID_SPI1,
  31        PERIPH_ID_SPI2,
  32        PERIPH_ID_SDMMC0 = 75,
  33        PERIPH_ID_SDMMC1,
  34        PERIPH_ID_SDMMC2,
  35        PERIPH_ID_SDMMC3,
  36        PERIPH_ID_I2C8 = 87,
  37        PERIPH_ID_I2C9,
  38        PERIPH_ID_I2S0 = 98,
  39        PERIPH_ID_I2S1 = 99,
  40
  41        /* Since following peripherals do
  42         * not have shared peripheral interrupts (SPIs)
  43         * they are numbered arbitiraly after the maximum
  44         * SPIs Exynos has (128)
  45         */
  46        PERIPH_ID_SROMC = 128,
  47        PERIPH_ID_SPI3,
  48        PERIPH_ID_SPI4,
  49        PERIPH_ID_SDMMC4,
  50        PERIPH_ID_PWM0,
  51        PERIPH_ID_PWM1,
  52        PERIPH_ID_PWM2,
  53        PERIPH_ID_PWM3,
  54        PERIPH_ID_PWM4,
  55        PERIPH_ID_I2C10 = 203,
  56
  57        PERIPH_ID_NONE = -1,
  58};
  59
  60#endif /* __ASM_ARM_ARCH_PERIPH_H */
  61