1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8#ifndef _MT7628_H_ 9#define _MT7628_H_ 10 11#define SYSCTL_BASE 0x10000000 12#define SYSCTL_SIZE 0x100 13#define MEMCTL_BASE 0x10000300 14#define MEMCTL_SIZE 0x100 15#define RBUSCTL_BASE 0x10000400 16#define RBUSCTL_SIZE 0x100 17#define RGCTL_BASE 0x10001000 18#define RGCTL_SIZE 0x800 19 20#define SYSCTL_EFUSE_CFG_REG 0x08 21#define EFUSE_MT7688 0x100000 22 23#define SYSCTL_CHIP_REV_ID_REG 0x0c 24#define PKG_ID 0x10000 25#define PKG_ID_AN 1 26#define PKG_ID_KN 0 27#define VER_S 8 28#define VER_M 0xf00 29#define ECO_S 0 30#define ECO_M 0x0f 31 32#define SYSCTL_SYSCFG0_REG 0x10 33#define XTAL_FREQ_SEL 0x40 34#define XTAL_40MHZ 1 35#define XTAL_25MHZ 0 36#define CHIP_MODE_S 1 37#define CHIP_MODE_M 0x0e 38#define DRAM_TYPE 0x01 39#define DRAM_DDR1 1 40#define DRAM_DDR2 0 41 42#define SYSCTL_ROM_STATUS_REG 0x28 43 44#define SYSCTL_CLKCFG0_REG 0x2c 45#define DIS_BBP_SLEEP 0x08 46#define EN_BBP_CLK 0x04 47#define CPU_PLL_FROM_BBP 0x02 48#define CPU_PLL_FROM_XTAL 0x01 49 50#define SYSCTL_RSTCTL_REG 0x34 51#define MC_RST 0x400 52 53#define SYSCTL_AGPIO_CFG_REG 0x3c 54#define EPHY_GPIO_AIO_EN_S 17 55#define EPHY_GPIO_AIO_EN_M 0x1e0000 56 57#define SYSCTL_GPIO_MODE1_REG 0x60 58#define UART2_MODE_S 26 59#define UART2_MODE_M 0xc000000 60#define UART1_MODE_S 24 61#define UART1_MODE_M 0x3000000 62#define UART0_MODE_S 8 63#define UART0_MODE_M 0x300 64#define SPIS_MODE_S 2 65#define SPIS_MODE_M 0x0c 66 67#define RBUSCTL_DYN_CFG0_REG 0x40 68#define CPU_FDIV_S 8 69#define CPU_FDIV_M 0xf00 70#define CPU_FFRAC_S 0 71#define CPU_FFRAC_M 0x0f 72 73#define RGCTL_PMU_G0_REG 0x100 74#define PMU_CFG_EN 0x80000000 75 76#define RGCTL_PMU_G1_REG 0x104 77#define RG_BUCK_FPWM 0x02 78 79#define RGCTL_PMU_G3_REG 0x10c 80#define NI_DDRLDO_STB 0x40000 81#define NI_DDRLDO_EN 0x10000 82#define RG_DDRLDO_VOSEL 0x40 83 84#define RGCTL_DDR_PAD_CK_G0_REG 0x700 85#define RGCTL_DDR_PAD_CMD_G0_REG 0x708 86#define RGCTL_DDR_PAD_DQ_G0_REG 0x710 87#define RGCTL_DDR_PAD_DQS_G0_REG 0x718 88#define RTT_S 8 89#define RTT_M 0x700 90 91#define RGCTL_DDR_PAD_CK_G1_REG 0x704 92#define RGCTL_DDR_PAD_CMD_G1_REG 0x70c 93#define RGCTL_DDR_PAD_DQ_G1_REG 0x714 94#define RGCTL_DDR_PAD_DQS_G1_REG 0x71c 95#define DRVP_S 0 96#define DRVP_M 0x0f 97#define DRVN_S 8 98#define DRVN_M 0xf00 99 100#ifndef __ASSEMBLY__ 101void mt7628_ddr_init(void); 102#endif 103 104#endif /* _MT7628_H_ */ 105