LXR uboot/arch/x86/cpu/braswell/fsp

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
   4 */
   5
   6#include <common.h>
   7#include <fdtdec.h>
   8#include <log.h>
   9#include <asm/fsp1/fsp_support.h>
  10#include <asm/global_data.h>
  11
  12DECLARE_GLOBAL_DATA_PTR;
  13
  14/**
  15 * Override the FSP's Azalia configuration data
  16 *
  17 * @azalia:     pointer to be updated to point to a ROM address where Azalia
  18 *              configuration data is stored
  19 */
  20__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
  21{
  22        *azalia = NULL;
  23}
  24
  25/**
  26 * Override the FSP's GPIO configuration data
  27 *
  28 * @family:     pointer to be updated to point to a ROM address where GPIO
  29 *              family configuration data is stored
  30 * @pad:        pointer to be updated to point to a ROM address where GPIO
  31 *              pad configuration data is stored
  32 */
  33__weak void update_fsp_gpio_configs(struct gpio_family **family,
  34                                    struct gpio_pad **pad)
  35{
  36        *family = NULL;
  37        *pad = NULL;
  38}
  39
  40/**
  41 * Override the FSP's configuration data.
  42 * If the device tree does not specify an integer setting, use the default
  43 * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
  44 */
  45void fsp_update_configs(struct fsp_config_data *config,
  46                        struct fspinit_rtbuf *rt_buf)
  47{
  48        struct upd_region *fsp_upd = &config->fsp_upd;
  49        struct memory_upd *memory_upd = &fsp_upd->memory_upd;
  50        struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
  51        const void *blob = gd->fdt_blob;
  52        int node;
  53
  54        /* Initialize runtime buffer for fsp_init() */
  55        rt_buf->common.stack_top = config->common.stack_top - 32;
  56        rt_buf->common.boot_mode = config->common.boot_mode;
  57        rt_buf->common.upd_data = &config->fsp_upd;
  58
  59        node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
  60        if (node < 0) {
  61                debug("%s: Cannot find FSP node\n", __func__);
  62                return;
  63        }
  64
  65        node = fdt_node_offset_by_compatible(blob, node,
  66                                             "intel,braswell-fsp-memory");
  67        if (node < 0) {
  68                debug("%s: Cannot find FSP memory node\n", __func__);
  69                return;
  70        }
  71
  72        /* Override memory UPD contents */
  73        memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
  74                "fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
  75        memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
  76                "fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
  77        memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
  78                "fsp,mrc-init-spd-addr1", 0xa0);
  79        memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
  80                "fsp,mrc-init-spd-addr2", 0xa2);
  81        memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
  82                "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
  83        memory_upd->aperture_size = fdtdec_get_int(blob, node,
  84                "fsp,aperture-size", APERTURE_SIZE_256MB);
  85        memory_upd->gtt_size = fdtdec_get_int(blob, node,
  86                "fsp,gtt-size", GTT_SIZE_1MB);
  87        memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
  88                "fsp,legacy-seg-decode");
  89        memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
  90                "fsp,enable-dvfs");
  91        memory_upd->memory_type = fdtdec_get_int(blob, node,
  92                "fsp,memory-type", DRAM_TYPE_DDR3);
  93        memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
  94                "fsp,enable-ca-mirror");
  95
  96        node = fdt_node_offset_by_compatible(blob, node,
  97                                             "intel,braswell-fsp-silicon");
  98        if (node < 0) {
  99                debug("%s: Cannot find FSP silicon node\n", __func__);
 100                return;
 101        }
 102
 103        /* Override silicon UPD contents */
 104        silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
 105                "fsp,sdcard-mode", SDCARD_MODE_PCI);
 106        silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
 107                "fsp,enable-hsuart0");
 108        silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
 109                "fsp,enable-hsuart1");
 110        silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
 111                "fsp,enable-azalia");
 112        if (silicon_upd->enable_azalia)
 113                update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
 114        silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
 115                "fsp,enable-sata");
 116        silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
 117                "fsp,enable-xhci");
 118        silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
 119                "fsp,lpe-mode", LPE_MODE_PCI);
 120        silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
 121                "fsp,enable-dma0");
 122        silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
 123                "fsp,enable-dma1");
 124        silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
 125                "fsp,enable-i2c0");
 126        silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
 127                "fsp,enable-i2c1");
 128        silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
 129                "fsp,enable-i2c2");
 130        silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
 131                "fsp,enable-i2c3");
 132        silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
 133                "fsp,enable-i2c4");
 134        silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
 135                "fsp,enable-i2c5");
 136        silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
 137                "fsp,enable-i2c6");
 138#ifdef CONFIG_HAVE_VBT
 139        silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
 140#endif
 141        update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
 142                                &silicon_upd->gpio_pad_ptr);
 143        /*
 144         * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
 145         * otherwise it just hangs in fsp_init().
 146         */
 147        if (gd->arch.x86_mask == 2)
 148                silicon_upd->disable_punit_pwr_config = 1;
 149        silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
 150                "fsp,emmc-mode", EMMC_MODE_PCI);
 151        silicon_upd->sata_speed = fdtdec_get_int(blob, node,
 152                "fsp,sata-speed", SATA_SPEED_GEN3);
 153        silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
 154                "fsp,pmic-i2c-bus", 0);
 155        silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
 156                "fsp,enable-isp");
 157        silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
 158                "fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
 159        silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
 160                "fsp,turbo-mode");
 161        silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
 162                "fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
 163        silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
 164                "fsp,sd-detect-chk");
 165}
 166