LXR uboot/arch/x86/cpu/lapic.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * From coreboot file of same name
   4 *
   5 * Copyright (C) 2008-2009 coresystems GmbH
   6 * Copyright (C) 2014 Google, Inc
   7 */
   8
   9#include <common.h>
  10#include <log.h>
  11#include <asm/io.h>
  12#include <asm/lapic.h>
  13#include <asm/msr.h>
  14#include <asm/msr-index.h>
  15#include <asm/post.h>
  16
  17unsigned long lapic_read(unsigned long reg)
  18{
  19        return readl(LAPIC_DEFAULT_BASE + reg);
  20}
  21
  22#define xchg(ptr, v)    ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
  23                                                    sizeof(*(ptr))))
  24
  25struct __xchg_dummy     { unsigned long a[100]; };
  26#define __xg(x)         ((struct __xchg_dummy *)(x))
  27
  28/*
  29 * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
  30 *
  31 * Note 2: xchg has side effect, so that attribute volatile is necessary,
  32 *         but generally the primitive is invalid, *ptr is output argument.
  33 */
  34static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
  35                                   int size)
  36{
  37        switch (size) {
  38        case 1:
  39                __asm__ __volatile__("xchgb %b0,%1"
  40                        : "=q" (x)
  41                        : "m" (*__xg(ptr)), "0" (x)
  42                        : "memory");
  43                break;
  44        case 2:
  45                __asm__ __volatile__("xchgw %w0,%1"
  46                        : "=r" (x)
  47                        : "m" (*__xg(ptr)), "0" (x)
  48                        : "memory");
  49                break;
  50        case 4:
  51                __asm__ __volatile__("xchgl %0,%1"
  52                        : "=r" (x)
  53                        : "m" (*__xg(ptr)), "0" (x)
  54                        : "memory");
  55                break;
  56        }
  57
  58        return x;
  59}
  60
  61void lapic_write(unsigned long reg, unsigned long v)
  62{
  63        (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
  64}
  65
  66void enable_lapic(void)
  67{
  68        if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
  69                msr_t msr;
  70
  71                msr = msr_read(MSR_IA32_APICBASE);
  72                msr.hi &= 0xffffff00;
  73                msr.lo |= MSR_IA32_APICBASE_ENABLE;
  74                msr.lo &= ~MSR_IA32_APICBASE_BASE;
  75                msr.lo |= LAPIC_DEFAULT_BASE;
  76                msr_write(MSR_IA32_APICBASE, msr);
  77        }
  78}
  79
  80void disable_lapic(void)
  81{
  82        if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
  83                msr_t msr;
  84
  85                msr = msr_read(MSR_IA32_APICBASE);
  86                msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
  87                msr_write(MSR_IA32_APICBASE, msr);
  88        }
  89}
  90
  91unsigned long lapicid(void)
  92{
  93        return lapic_read(LAPIC_ID) >> 24;
  94}
  95
  96static void lapic_wait_icr_idle(void)
  97{
  98        do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
  99}
 100
 101int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 102{
 103        int timeout;
 104        unsigned long status;
 105        int result;
 106
 107        lapic_wait_icr_idle();
 108        lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 109        lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
 110
 111        timeout = 0;
 112        do {
 113                status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
 114        } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
 115
 116        result = -1;
 117        if (status == LAPIC_ICR_RR_VALID) {
 118                *pvalue = lapic_read(LAPIC_RRR);
 119                result = 0;
 120        }
 121
 122        return result;
 123}
 124
 125void lapic_setup(void)
 126{
 127        /* Only Pentium Pro and later have those MSR stuff */
 128        debug("Setting up local apic: ");
 129
 130        /* Enable the local apic */
 131        enable_lapic();
 132
 133        /* Set Task Priority to 'accept all' */
 134        lapic_write(LAPIC_TASKPRI,
 135                    lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
 136
 137        /* Put the local apic in virtual wire mode */
 138        lapic_write(LAPIC_SPIV, (lapic_read(LAPIC_SPIV) &
 139                    ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
 140        lapic_write(LAPIC_LVT0, (lapic_read(LAPIC_LVT0) &
 141                    ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
 142                    LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
 143                    LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
 144                    LAPIC_DELIVERY_MODE_MASK)) |
 145                    (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
 146                    LAPIC_DELIVERY_MODE_EXTINT));
 147        lapic_write(LAPIC_LVT1, (lapic_read(LAPIC_LVT1) &
 148                    ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
 149                    LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
 150                    LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
 151                    LAPIC_DELIVERY_MODE_MASK)) |
 152                    (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
 153                    LAPIC_DELIVERY_MODE_NMI));
 154
 155        debug("apic_id: 0x%02lx, ", lapicid());
 156
 157        debug("done.\n");
 158        post_code(POST_LAPIC);
 159}
 160