LXR uboot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017 Microchip Corporation
   4 *                    Wenyou Yang <wenyou.yang@microchip.com>
   5 */
   6
   7#include <common.h>
   8#include <debug_uart.h>
   9#include <dm.h>
  10#include <i2c.h>
  11#include <init.h>
  12#include <nand.h>
  13#include <asm/global_data.h>
  14#include <asm/io.h>
  15#include <asm/arch/at91_common.h>
  16#include <asm/arch/atmel_pio4.h>
  17#include <asm/arch/atmel_mpddrc.h>
  18#include <asm/arch/atmel_sdhci.h>
  19#include <asm/arch/clk.h>
  20#include <asm/arch/gpio.h>
  21#include <asm/arch/sama5d2.h>
  22#include <asm/arch/sama5d2_smc.h>
  23
  24extern void at91_pda_detect(void);
  25
  26DECLARE_GLOBAL_DATA_PTR;
  27
  28static void rgb_leds_init(void)
  29{
  30        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 0);       /* LED RED */
  31        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 8, 0);        /* LED GREEN */
  32        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 6, 1);        /* LED BLUE */
  33}
  34
  35#ifdef CONFIG_NAND_ATMEL
  36static void board_nand_hw_init(void)
  37{
  38        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  39
  40        at91_periph_clk_enable(ATMEL_ID_HSMC);
  41
  42        /* Configure SMC CS3 for NAND */
  43        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  44               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  45               &smc->cs[3].setup);
  46        writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
  47               AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  48               &smc->cs[3].pulse);
  49        writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
  50               &smc->cs[3].cycle);
  51        writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  52               AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  53               AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
  54               AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  55        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  56               AT91_SMC_MODE_EXNW_DISABLE |
  57               AT91_SMC_MODE_DBW_8 |
  58               AT91_SMC_MODE_TDF_CYCLE(3),
  59               &smc->cs[3].mode);
  60
  61        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME);       /* D0 */
  62        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME);       /* D1 */
  63        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME);       /* D2 */
  64        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME);       /* D3 */
  65        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME);       /* D4 */
  66        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME);       /* D5 */
  67        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME);       /* D6 */
  68        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME);       /* D7 */
  69        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0);  /* RE */
  70        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
  71        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK);       /* NCS */
  72        atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK);        /* RDY */
  73        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK);        /* ALE */
  74        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK);        /* CLE */
  75}
  76#endif
  77
  78#ifdef CONFIG_BOARD_LATE_INIT
  79int board_late_init(void)
  80{
  81        at91_pda_detect();
  82        return 0;
  83}
  84#endif
  85
  86#ifdef CONFIG_CMD_USB
  87static void board_usb_hw_init(void)
  88{
  89        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
  90}
  91#endif
  92
  93#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  94static void board_uart0_hw_init(void)
  95{
  96        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK);       /* URXD0 */
  97        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  98
  99        at91_periph_clk_enable(ATMEL_ID_UART0);
 100}
 101
 102void board_debug_uart_init(void)
 103{
 104        board_uart0_hw_init();
 105}
 106#endif
 107
 108#ifdef CONFIG_BOARD_EARLY_INIT_F
 109int board_early_init_f(void)
 110{
 111#ifdef CONFIG_DEBUG_UART
 112        debug_uart_init();
 113#endif
 114        return 0;
 115}
 116#endif
 117
 118int board_init(void)
 119{
 120        /* address of boot parameters */
 121        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 122
 123        rgb_leds_init();
 124
 125#ifdef CONFIG_NAND_ATMEL
 126        board_nand_hw_init();
 127#endif
 128#ifdef CONFIG_CMD_USB
 129        board_usb_hw_init();
 130#endif
 131        return 0;
 132}
 133
 134int dram_init(void)
 135{
 136        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 137                                    CONFIG_SYS_SDRAM_SIZE);
 138        return 0;
 139}
 140
 141#define AT24MAC_MAC_OFFSET      0xfa
 142
 143#ifdef CONFIG_MISC_INIT_R
 144int misc_init_r(void)
 145{
 146#ifdef CONFIG_I2C_EEPROM
 147        at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 148#endif
 149        return 0;
 150}
 151#endif
 152