LXR uboot/board/freescale/ls1088a/ddr.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2017 NXP
   4 */
   5
   6#include <common.h>
   7#include <fsl_ddr_sdram.h>
   8#include <fsl_ddr_dimm_params.h>
   9#include <log.h>
  10#include <asm/arch/soc.h>
  11#include <asm/arch/clock.h>
  12#include <asm/global_data.h>
  13#include "ddr.h"
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  18static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
  19{
  20        int vdd;
  21
  22        vdd = get_core_volt_from_fuse();
  23        /* Nothing to do for silicons doesn't support VID */
  24        if (vdd < 0)
  25                return;
  26
  27        if (vdd == 900) {
  28                popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
  29                debug("VID: configure DDR to support 900 mV\n");
  30        }
  31}
  32#endif
  33
  34void fsl_ddr_board_options(memctl_options_t *popts,
  35                           dimm_params_t *pdimm,
  36                           unsigned int ctrl_num)
  37{
  38        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  39        ulong ddr_freq;
  40
  41        if (ctrl_num > 1) {
  42                printf("Not supported controller number %d\n", ctrl_num);
  43                return;
  44        }
  45        if (!pdimm->n_ranks)
  46                return;
  47
  48        /*
  49         * we use identical timing for all slots. If needed, change the code
  50         * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  51         */
  52        pbsp = udimms[0];
  53
  54        /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  55         * freqency and n_banks specified in board_specific_parameters table.
  56         */
  57        ddr_freq = get_ddr_freq(0) / 1000000;
  58        while (pbsp->datarate_mhz_high) {
  59                if (pbsp->n_ranks == pdimm->n_ranks) {
  60                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  61                                popts->clk_adjust = pbsp->clk_adjust;
  62                                popts->wrlvl_start = pbsp->wrlvl_start;
  63                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  64                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  65                                goto found;
  66                        }
  67                        pbsp_highest = pbsp;
  68                }
  69                pbsp++;
  70        }
  71
  72        if (pbsp_highest) {
  73                printf("Error: board specific timing not found for %lu MT/s\n",
  74                       ddr_freq);
  75                printf("Trying to use the highest speed (%u) parameters\n",
  76                       pbsp_highest->datarate_mhz_high);
  77                popts->clk_adjust = pbsp_highest->clk_adjust;
  78                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  79                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  80                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  81        } else {
  82                panic("DIMM is not supported by this board");
  83        }
  84found:
  85        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  86                "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  87                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  88                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  89                pbsp->wrlvl_ctl_3);
  90
  91        popts->half_strength_driver_enable = 0;
  92        /*
  93         * Write leveling override
  94         */
  95        popts->wrlvl_override = 1;
  96        popts->wrlvl_sample = 0xf;
  97
  98
  99        /* Enable ZQ calibration */
 100        popts->zq_en = 1;
 101
 102        /* Enable DDR hashing */
 103        popts->addr_hash = 1;
 104
 105        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
 106#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 107        fsl_ddr_setup_0v9_volt(popts);
 108#endif
 109
 110        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
 111                          DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
 112}
 113
 114#ifdef CONFIG_TFABOOT
 115int fsl_initdram(void)
 116{
 117        gd->ram_size = tfa_get_dram_size();
 118
 119        if (!gd->ram_size)
 120                gd->ram_size = fsl_ddr_sdram_size();
 121
 122        return 0;
 123}
 124#else
 125int fsl_initdram(void)
 126{
 127        puts("Initializing DDR....using SPD\n");
 128
 129#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 130        gd->ram_size = fsl_ddr_sdram_size();
 131#else
 132        gd->ram_size = fsl_ddr_sdram();
 133#endif
 134        return 0;
 135}
 136#endif /* CONFIG_TFABOOT */
 137