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6#include <common.h>
7#include <clock_legacy.h>
8#include <env.h>
9#include <init.h>
10#include <malloc.h>
11#include <errno.h>
12#include <netdev.h>
13#include <fsl_ifc.h>
14#include <fsl_ddr.h>
15#include <asm/global_data.h>
16#include <asm/io.h>
17#include <fdt_support.h>
18#include <linux/libfdt.h>
19#include <fsl-mc/fsl_mc.h>
20#include <env_internal.h>
21#include <i2c.h>
22#include <rtc.h>
23#include <asm/arch/soc.h>
24#include <hwconfig.h>
25#include <asm/arch/ppa.h>
26#include <asm/arch-fsl-layerscape/fsl_icid.h>
27#include "../common/i2c_mux.h"
28
29#include "../common/qixis.h"
30#include "ls2080aqds_qixis.h"
31#include "../common/vid.h"
32
33#define PIN_MUX_SEL_SDHC 0x00
34#define PIN_MUX_SEL_DSPI 0x0a
35#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
36
37#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
38
39DECLARE_GLOBAL_DATA_PTR;
40
41enum {
42 MUX_TYPE_SDHC,
43 MUX_TYPE_DSPI,
44};
45
46unsigned long long get_qixis_addr(void)
47{
48 unsigned long long addr;
49
50 if (gd->flags & GD_FLG_RELOC)
51 addr = QIXIS_BASE_PHYS;
52 else
53 addr = QIXIS_BASE_PHYS_EARLY;
54
55
56
57
58
59 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
60
61 return addr;
62}
63
64int checkboard(void)
65{
66 char buf[64];
67 u8 sw;
68 static const char *const freq[] = {"100", "125", "156.25",
69 "100 separate SSCG"};
70 int clock;
71
72 cpu_name(buf);
73 printf("Board: %s-QDS, ", buf);
74
75 sw = QIXIS_READ(arch);
76 printf("Board Arch: V%d, ", sw >> 4);
77 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
78
79 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
80
81 sw = QIXIS_READ(brdcfg[0]);
82 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
83
84 if (sw < 0x8)
85 printf("vBank: %d\n", sw);
86 else if (sw == 0x8)
87 puts("PromJet\n");
88 else if (sw == 0x9)
89 puts("NAND\n");
90 else if (sw == 0xf)
91 puts("QSPI\n");
92 else if (sw == 0x15)
93 printf("IFCCard\n");
94 else
95 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
96
97 printf("FPGA: v%d (%s), build %d",
98 (int)QIXIS_READ(scver), qixis_read_tag(buf),
99 (int)qixis_read_minor());
100
101 printf(" on %s", qixis_read_time(buf));
102
103
104
105
106
107
108
109
110
111 puts("SERDES1 Reference : ");
112 sw = QIXIS_READ(brdcfg[2]);
113 clock = (sw >> 6) & 3;
114 printf("Clock1 = %sMHz ", freq[clock]);
115 clock = (sw >> 4) & 3;
116 printf("Clock2 = %sMHz", freq[clock]);
117
118 puts("\nSERDES2 Reference : ");
119 clock = (sw >> 2) & 3;
120 printf("Clock1 = %sMHz ", freq[clock]);
121 clock = (sw >> 0) & 3;
122 printf("Clock2 = %sMHz\n", freq[clock]);
123
124 return 0;
125}
126
127unsigned long get_board_sys_clk(void)
128{
129 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
130
131 switch (sysclk_conf & 0x0F) {
132 case QIXIS_SYSCLK_83:
133 return 83333333;
134 case QIXIS_SYSCLK_100:
135 return 100000000;
136 case QIXIS_SYSCLK_125:
137 return 125000000;
138 case QIXIS_SYSCLK_133:
139 return 133333333;
140 case QIXIS_SYSCLK_150:
141 return 150000000;
142 case QIXIS_SYSCLK_160:
143 return 160000000;
144 case QIXIS_SYSCLK_166:
145 return 166666666;
146 }
147 return 66666666;
148}
149
150unsigned long get_board_ddr_clk(void)
151{
152 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
153
154 switch ((ddrclk_conf & 0x30) >> 4) {
155 case QIXIS_DDRCLK_100:
156 return 100000000;
157 case QIXIS_DDRCLK_125:
158 return 125000000;
159 case QIXIS_DDRCLK_133:
160 return 133333333;
161 }
162 return 66666666;
163}
164
165int config_board_mux(int ctrl_type)
166{
167 u8 reg5;
168
169 reg5 = QIXIS_READ(brdcfg[5]);
170
171 switch (ctrl_type) {
172 case MUX_TYPE_SDHC:
173 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
174 break;
175 case MUX_TYPE_DSPI:
176 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
177 break;
178 default:
179 printf("Wrong mux interface type\n");
180 return -1;
181 }
182
183 QIXIS_WRITE(brdcfg[5], reg5);
184
185 return 0;
186}
187
188int board_init(void)
189{
190 char *env_hwconfig;
191 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
192 u32 val;
193
194 init_final_memctl_regs();
195
196 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
197
198 env_hwconfig = env_get("hwconfig");
199
200 if (hwconfig_f("dspi", env_hwconfig) &&
201 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
202 config_board_mux(MUX_TYPE_DSPI);
203 else
204 config_board_mux(MUX_TYPE_SDHC);
205
206#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
207 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
208
209 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
210 QIXIS_WRITE(brdcfg[9],
211 (QIXIS_READ(brdcfg[9]) & 0xf8) |
212 FSL_QIXIS_BRDCFG9_QSPI);
213#endif
214
215 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
216
217#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
218#if CONFIG_IS_ENABLED(DM_I2C)
219 rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
220#else
221 rtc_enable_32khz_output();
222#endif
223#endif
224
225#ifdef CONFIG_FSL_LS_PPA
226 ppa_init();
227#endif
228
229#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
230 pci_init();
231#endif
232
233 return 0;
234}
235
236int board_early_init_f(void)
237{
238#if defined(CONFIG_SYS_I2C_EARLY_INIT)
239 i2c_early_init_f();
240#endif
241 fsl_lsch3_early_init_f();
242#ifdef CONFIG_FSL_QSPI
243
244 out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
245#endif
246 return 0;
247}
248
249int misc_init_r(void)
250{
251 if (adjust_vdd(0))
252 printf("Warning: Adjusting core voltage failed.\n");
253
254 return 0;
255}
256
257void detail_board_ddr_info(void)
258{
259 puts("\nDDR ");
260 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
261 print_ddr_info(0);
262#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
263 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
264 puts("\nDP-DDR ");
265 print_size(gd->bd->bi_dram[2].size, "");
266 print_ddr_info(CONFIG_DP_DDR_CTRL);
267 }
268#endif
269}
270
271#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
272void fdt_fixup_board_enet(void *fdt)
273{
274 int offset;
275
276 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
277
278 if (offset < 0)
279 offset = fdt_path_offset(fdt, "/fsl-mc");
280
281 if (offset < 0) {
282 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
283 __func__, offset);
284 return;
285 }
286
287 if (get_mc_boot_status() == 0 &&
288 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
289 fdt_status_okay(fdt, offset);
290 else
291 fdt_status_fail(fdt, offset);
292}
293
294void board_quiesce_devices(void)
295{
296 fsl_mc_ldpaa_exit(gd->bd);
297}
298#endif
299
300#ifdef CONFIG_OF_BOARD_SETUP
301int ft_board_setup(void *blob, struct bd_info *bd)
302{
303 u64 base[CONFIG_NR_DRAM_BANKS];
304 u64 size[CONFIG_NR_DRAM_BANKS];
305
306 ft_cpu_setup(blob, bd);
307
308
309 base[0] = gd->bd->bi_dram[0].start;
310 size[0] = gd->bd->bi_dram[0].size;
311 base[1] = gd->bd->bi_dram[1].start;
312 size[1] = gd->bd->bi_dram[1].size;
313
314#ifdef CONFIG_RESV_RAM
315
316 if (gd->arch.resv_ram >= base[0] &&
317 gd->arch.resv_ram < base[0] + size[0])
318 size[0] = gd->arch.resv_ram - base[0];
319 else if (gd->arch.resv_ram >= base[1] &&
320 gd->arch.resv_ram < base[1] + size[1])
321 size[1] = gd->arch.resv_ram - base[1];
322#endif
323
324 fdt_fixup_memory_banks(blob, base, size, 2);
325
326 fdt_fsl_mc_fixup_iommu_map_entry(blob);
327
328 fsl_fdt_fixup_dr_usb(blob, bd);
329
330#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
331 fdt_fixup_board_enet(blob);
332#endif
333
334 fdt_fixup_icid(blob);
335
336 return 0;
337}
338#endif
339
340void qixis_dump_switch(void)
341{
342 int i, nr_of_cfgsw;
343
344 QIXIS_WRITE(cms[0], 0x00);
345 nr_of_cfgsw = QIXIS_READ(cms[1]);
346
347 puts("DIP switch settings dump:\n");
348 for (i = 1; i <= nr_of_cfgsw; i++) {
349 QIXIS_WRITE(cms[0], i);
350 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
351 }
352}
353
