1
2
3
4
5
6
7
8#include <common.h>
9#include <cpu_func.h>
10#include <init.h>
11#include <malloc.h>
12#include <dm/platform_data/serial_sh.h>
13#include <asm/processor.h>
14#include <asm/mach-types.h>
15#include <asm/io.h>
16#include <linux/bitops.h>
17#include <linux/errno.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/gpio.h>
20#include <asm/arch/rmobile.h>
21#include <asm/arch/rcar-mstp.h>
22
23#include <spl.h>
24
25#define TMU0_MSTP125 BIT(25)
26#define SCIF0_MSTP721 BIT(21)
27#define QSPI_MSTP917 BIT(17)
28
29#define SD2CKCR 0xE615026C
30#define SD_97500KHZ 0x7
31
32struct reg_config {
33 u16 off;
34 u32 val;
35};
36
37static void dbsc_wait(u16 reg)
38{
39 static const u32 dbsc3_0_base = DBSC3_0_BASE;
40
41 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
42 ;
43}
44
45static void spl_init_sys(void)
46{
47 u32 r0 = 0;
48
49 writel(0xa5a5a500, 0xe6020004);
50 writel(0xa5a5a500, 0xe6030004);
51
52 asm volatile(
53
54 "mcr 15, 0, %0, cr7, cr5, 0 \n"
55
56 "mcr 15, 0, %0, cr7, cr5, 6 \n"
57
58 "mrc 15, 0, %0, cr1, cr0, 0 \n"
59 "orr %0, #0x1800 \n"
60 "mcr 15, 0, %0, cr1, cr0, 0 \n"
61 "isb sy \n"
62 :"=r"(r0));
63}
64
65static void spl_init_pfc(void)
66{
67 static const struct reg_config pfc_with_unlock[] = {
68 { 0x0090, 0x60000000 },
69 { 0x0094, 0x60000000 },
70 { 0x0098, 0x00800200 },
71 { 0x009c, 0x00000000 },
72 { 0x0020, 0x00000000 },
73 { 0x0024, 0x00000000 },
74 { 0x0028, 0x000244c8 },
75 { 0x002c, 0x00000000 },
76 { 0x0030, 0x00002400 },
77 { 0x0034, 0x01520000 },
78 { 0x0038, 0x00724003 },
79 { 0x003c, 0x00000000 },
80 { 0x0040, 0x00000000 },
81 { 0x0044, 0x00000000 },
82 { 0x0048, 0x00000000 },
83 { 0x004c, 0x00000000 },
84 { 0x0050, 0x00000000 },
85 { 0x0054, 0x00000000 },
86 { 0x0058, 0x00000000 },
87 { 0x005c, 0x00000000 },
88 { 0x0160, 0x00000000 },
89 { 0x0004, 0xffffffff },
90 { 0x0008, 0x00ec3fff },
91 { 0x000c, 0x3bc001e7 },
92 { 0x0010, 0x5bffffff },
93 { 0x0014, 0x1ffffffb },
94 { 0x0018, 0x01bffff0 },
95 { 0x001c, 0xcf7fffff },
96 { 0x0074, 0x0381fc00 },
97 };
98
99 static const struct reg_config pfc_without_unlock[] = {
100 { 0x0100, 0xffffffdf },
101 { 0x0104, 0xc883c3ff },
102 { 0x0108, 0x1201f3c9 },
103 { 0x010c, 0x00000000 },
104 { 0x0110, 0xffffeb04 },
105 { 0x0114, 0xc003ffff },
106 { 0x0118, 0x0800000f },
107 { 0x011c, 0x001800f0 },
108 };
109
110 static const u32 pfc_base = 0xe6060000;
111
112 unsigned int i;
113
114 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
115 writel(~pfc_with_unlock[i].val, pfc_base);
116 writel(pfc_with_unlock[i].val,
117 pfc_base | pfc_with_unlock[i].off);
118 }
119
120 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
121 writel(pfc_without_unlock[i].val,
122 pfc_base | pfc_without_unlock[i].off);
123}
124
125static void spl_init_gpio(void)
126{
127 static const u16 gpio_offs[] = {
128 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
129 };
130
131 static const struct reg_config gpio_set[] = {
132 { 0x2000, 0x04381000 },
133 { 0x5000, 0x00000000 },
134 { 0x5800, 0x000e0000 },
135 };
136
137 static const struct reg_config gpio_clr[] = {
138 { 0x1000, 0x00000000 },
139 { 0x2000, 0x04381010 },
140 { 0x3000, 0x00000000 },
141 { 0x4000, 0x00000000 },
142 { 0x5000, 0x00400000 },
143 { 0x5400, 0x00000000 },
144 { 0x5800, 0x000e0380 },
145 };
146
147 static const u32 gpio_base = 0xe6050000;
148
149 unsigned int i;
150
151 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
152 writel(0, gpio_base | 0x20 | gpio_offs[i]);
153
154 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
155 writel(0, gpio_base | 0x00 | gpio_offs[i]);
156
157 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
158 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
159
160 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
161 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
162}
163
164static void spl_init_lbsc(void)
165{
166 static const struct reg_config lbsc_config[] = {
167 { 0x00, 0x00000020 },
168 { 0x08, 0x00002020 },
169 { 0x30, 0x2a103320 },
170 { 0x38, 0xff70ff70 },
171 };
172
173 static const u16 lbsc_offs[] = {
174 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
175 };
176
177 static const u32 lbsc_base = 0xfec00200;
178
179 unsigned int i;
180
181 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
182 writel(lbsc_config[i].val,
183 lbsc_base | lbsc_config[i].off);
184 writel(lbsc_config[i].val,
185 lbsc_base | (lbsc_config[i].off + 4));
186 }
187
188 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
189 writel(0, lbsc_base | lbsc_offs[i]);
190}
191
192static void spl_init_dbsc(void)
193{
194 static const struct reg_config dbsc_config1[] = {
195 { 0x0280, 0x0000a55a },
196 { 0x0018, 0x21000000 },
197 { 0x0018, 0x11000000 },
198 { 0x0018, 0x10000000 },
199 { 0x0290, 0x00000001 },
200 { 0x02a0, 0x80000000 },
201 { 0x0290, 0x00000004 },
202 };
203
204 static const struct reg_config dbsc_config2[] = {
205 { 0x0290, 0x00000006 },
206 { 0x02a0, 0x0001c000 },
207 };
208
209 static const struct reg_config dbsc_config4[] = {
210 { 0x0290, 0x00000010 },
211 { 0x02a0, 0xf00464db },
212 { 0x0290, 0x00000061 },
213 { 0x02a0, 0x0000006d },
214 { 0x0290, 0x00000001 },
215 { 0x02a0, 0x00000073 },
216 { 0x0020, 0x00000007 },
217 { 0x0024, 0x0f030a02 },
218 { 0x0030, 0x00000001 },
219 { 0x00b0, 0x00000000 },
220 { 0x0040, 0x0000000b },
221 { 0x0044, 0x00000008 },
222 { 0x0048, 0x00000000 },
223 { 0x0050, 0x0000000b },
224 { 0x0054, 0x000c000b },
225 { 0x0058, 0x00000027 },
226 { 0x005c, 0x0000001c },
227 { 0x0060, 0x00000006 },
228 { 0x0064, 0x00000020 },
229 { 0x0068, 0x00000008 },
230 { 0x006c, 0x0000000c },
231 { 0x0070, 0x00000009 },
232 { 0x0074, 0x00000012 },
233 { 0x0078, 0x000000d0 },
234 { 0x007c, 0x00140005 },
235 { 0x0080, 0x00050004 },
236 { 0x0084, 0x70233005 },
237 { 0x0088, 0x000c0000 },
238 { 0x008c, 0x00000200 },
239 { 0x0090, 0x00000040 },
240 { 0x0100, 0x00000001 },
241 { 0x00c0, 0x00020001 },
242 { 0x00c8, 0x20042004 },
243 { 0x0380, 0x00020002 },
244 { 0x0390, 0x0000001f },
245 };
246
247 static const struct reg_config dbsc_config5[] = {
248 { 0x0244, 0x00000011 },
249 { 0x0290, 0x00000003 },
250 { 0x02a0, 0x0300c561 },
251 { 0x0290, 0x00000023 },
252 { 0x02a0, 0x00fcdb60 },
253 { 0x0290, 0x00000011 },
254 { 0x02a0, 0x1000040b },
255 { 0x0290, 0x00000012 },
256 { 0x02a0, 0x9d9cbb66 },
257 { 0x0290, 0x00000013 },
258 { 0x02a0, 0x1a868400 },
259 { 0x0290, 0x00000014 },
260 { 0x02a0, 0x300214d8 },
261 { 0x0290, 0x00000015 },
262 { 0x02a0, 0x00000d70 },
263 { 0x0290, 0x00000016 },
264 { 0x02a0, 0x00000006 },
265 { 0x0290, 0x00000017 },
266 { 0x02a0, 0x00000018 },
267 { 0x0290, 0x0000001a },
268 { 0x02a0, 0x910035c7 },
269 { 0x0290, 0x00000004 },
270 };
271
272 static const struct reg_config dbsc_config6[] = {
273 { 0x0290, 0x00000001 },
274 { 0x02a0, 0x00000181 },
275 { 0x0018, 0x11000000 },
276 { 0x0290, 0x00000004 },
277 };
278
279 static const struct reg_config dbsc_config7[] = {
280 { 0x0290, 0x00000001 },
281 { 0x02a0, 0x0000fe01 },
282 { 0x0304, 0x00000000 },
283 { 0x00f4, 0x01004c20 },
284 { 0x00f8, 0x014000aa },
285 { 0x00e0, 0x00000140 },
286 { 0x00e4, 0x00081860 },
287 { 0x00e8, 0x00010000 },
288 { 0x0290, 0x00000004 },
289 };
290
291 static const struct reg_config dbsc_config8[] = {
292 { 0x0014, 0x00000001 },
293 { 0x0010, 0x00000001 },
294 { 0x0280, 0x00000000 },
295 };
296
297 static const u32 dbsc3_0_base = DBSC3_0_BASE;
298 unsigned int i;
299
300 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
301 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
302
303 dbsc_wait(0x2a0);
304
305 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
306 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
307
308 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
309 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
310
311 dbsc_wait(0x240);
312
313 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
314 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
315
316 dbsc_wait(0x2a0);
317
318 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
319 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
320
321 dbsc_wait(0x2a0);
322
323 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
324 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
325
326 dbsc_wait(0x2a0);
327
328 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
329 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
330
331}
332
333static void spl_init_qspi(void)
334{
335 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
336
337 static const u32 qspi_base = 0xe6b10000;
338
339 writeb(0x08, qspi_base + 0x00);
340 writeb(0x00, qspi_base + 0x01);
341 writeb(0x06, qspi_base + 0x02);
342 writeb(0x01, qspi_base + 0x0a);
343 writeb(0x00, qspi_base + 0x0b);
344 writeb(0x00, qspi_base + 0x0c);
345 writeb(0x00, qspi_base + 0x0d);
346 writeb(0x00, qspi_base + 0x0e);
347
348 writew(0xe080, qspi_base + 0x10);
349
350 writeb(0xc0, qspi_base + 0x18);
351 writeb(0x00, qspi_base + 0x18);
352 writeb(0x00, qspi_base + 0x08);
353 writeb(0x48, qspi_base + 0x00);
354}
355
356void board_init_f(ulong dummy)
357{
358 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
359 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
360
361
362
363
364
365 writel(SD_97500KHZ, SD2CKCR);
366
367 spl_init_sys();
368 spl_init_pfc();
369 spl_init_gpio();
370 spl_init_lbsc();
371 spl_init_dbsc();
372 spl_init_qspi();
373}
374
375void spl_board_init(void)
376{
377
378 preloader_console_init();
379}
380
381void board_boot_order(u32 *spl_boot_list)
382{
383 const u32 jtag_magic = 0x1337c0de;
384 const u32 load_magic = 0xb33fc0de;
385
386
387
388
389
390 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
391 printf("JTAG boot detected!\n");
392
393 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
394 ;
395
396 spl_boot_list[0] = BOOT_DEVICE_RAM;
397 spl_boot_list[1] = BOOT_DEVICE_NONE;
398
399 return;
400 }
401
402
403 spl_boot_list[0] = BOOT_DEVICE_SPI;
404 spl_boot_list[1] = BOOT_DEVICE_UART;
405 spl_boot_list[2] = BOOT_DEVICE_NONE;
406}
407
408void reset_cpu(void)
409{
410}
411
