LXR uboot/board/ronetix/pm9g45/pm9g45.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2010
   4 * Ilko Iliev <iliev@ronetix.at>
   5 * Asen Dimov <dimov@ronetix.at>
   6 * Ronetix GmbH <www.ronetix.at>
   7 *
   8 * (C) Copyright 2007-2008
   9 * Stelian Pop <stelian@popies.net>
  10 * Lead Tech Design <www.leadtechdesign.com>
  11 */
  12
  13#include <common.h>
  14#include <init.h>
  15#include <asm/global_data.h>
  16#include <linux/sizes.h>
  17#include <asm/io.h>
  18#include <asm/gpio.h>
  19#include <asm/arch/at91sam9_smc.h>
  20#include <asm/arch/at91_common.h>
  21#include <asm/arch/at91_rstc.h>
  22#include <asm/arch/at91_matrix.h>
  23#include <asm/arch/gpio.h>
  24#include <asm/arch/clk.h>
  25#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  26#include <net.h>
  27#endif
  28#include <netdev.h>
  29#include <asm/mach-types.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33/*
  34 * Miscelaneous platform dependent initialisations
  35 */
  36
  37#ifdef CONFIG_CMD_NAND
  38static void pm9g45_nand_hw_init(void)
  39{
  40        unsigned long csa;
  41        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  42        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  43
  44        /* Enable CS3 */
  45        csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
  46        writel(csa, &matrix->ccr[6]);
  47
  48        /* Configure SMC CS3 for NAND/SmartMedia */
  49        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  50                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  51                &smc->cs[3].setup);
  52
  53        writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  54                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  55                &smc->cs[3].pulse);
  56
  57        writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  58                &smc->cs[3].cycle);
  59
  60        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  61                AT91_SMC_MODE_EXNW_DISABLE |
  62                AT91_SMC_MODE_DBW_8 |
  63                AT91_SMC_MODE_TDF_CYCLE(3),
  64                &smc->cs[3].mode);
  65
  66        at91_periph_clk_enable(ATMEL_ID_PIOC);
  67
  68#ifdef CONFIG_SYS_NAND_READY_PIN
  69        /* Configure RDY/BSY */
  70        gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  71#endif
  72
  73        /* Enable NandFlash */
  74        gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  75}
  76#endif
  77
  78#ifdef CONFIG_MACB
  79static void pm9g45_macb_hw_init(void)
  80{
  81        /*
  82         * PD2 enables the 50MHz oscillator for Ethernet PHY
  83         * 1 - enable
  84         * 0 - disable
  85         */
  86        at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
  87        at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
  88
  89        at91_periph_clk_enable(ATMEL_ID_EMAC);
  90
  91        /*
  92         * Disable pull-up on:
  93         *      RXDV (PA15) => PHY normal mode (not Test mode)
  94         *      ERX0 (PA12) => PHY ADDR0
  95         *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  96         *
  97         * PHY has internal pull-down
  98         */
  99        at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
 100        at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
 101        at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
 102
 103        /* Re-enable pull-up */
 104        at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
 105        at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
 106        at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
 107
 108        at91_macb_hw_init();
 109}
 110#endif
 111
 112int board_early_init_f(void)
 113{
 114        at91_periph_clk_enable(ATMEL_ID_PIOA);
 115        at91_periph_clk_enable(ATMEL_ID_PIOB);
 116        at91_periph_clk_enable(ATMEL_ID_PIOC);
 117        at91_periph_clk_enable(ATMEL_ID_PIODE);
 118
 119        at91_seriald_hw_init();
 120
 121        return 0;
 122}
 123
 124int board_init(void)
 125{
 126        /* arch number of AT91SAM9M10G45EK-Board */
 127        gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
 128        /* adress of boot parameters */
 129        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 130
 131#ifdef CONFIG_CMD_NAND
 132        pm9g45_nand_hw_init();
 133#endif
 134
 135#ifdef CONFIG_MACB
 136        pm9g45_macb_hw_init();
 137#endif
 138        return 0;
 139}
 140
 141int dram_init(void)
 142{
 143        /* dram_init must store complete ramsize in gd->ram_size */
 144        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 145                                    CONFIG_SYS_SDRAM_SIZE);
 146        return 0;
 147}
 148
 149int dram_init_banksize(void)
 150{
 151        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 152        gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
 153
 154        return 0;
 155}
 156
 157#ifdef CONFIG_RESET_PHY_R
 158void reset_phy(void)
 159{
 160#ifdef CONFIG_MACB
 161        /*
 162         * Initialize ethernet HW addr prior to starting Linux,
 163         * needed for nfsroot
 164         */
 165        eth_init();
 166#endif
 167}
 168#endif
 169
 170int board_eth_init(struct bd_info *bis)
 171{
 172        int rc = 0;
 173#ifdef CONFIG_MACB
 174        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
 175#endif
 176        return rc;
 177}
 178