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9#include <common.h>
10#include <image.h>
11#include <init.h>
12#include <asm/arch/ddr3.h>
13#include <asm/arch/hardware.h>
14#include <asm/ti-common/keystone_net.h>
15
16unsigned int get_external_clk(u32 clk)
17{
18 unsigned int clk_freq;
19
20 switch (clk) {
21 case sys_clk:
22 clk_freq = 122880000;
23 break;
24 case alt_core_clk:
25 clk_freq = 100000000;
26 break;
27 case pa_clk:
28 clk_freq = 122880000;
29 break;
30 case tetris_clk:
31 clk_freq = 122880000;
32 break;
33 case ddr3a_clk:
34 clk_freq = 100000000;
35 break;
36 default:
37 clk_freq = 0;
38 break;
39 }
40
41 return clk_freq;
42}
43
44static struct pll_init_data core_pll_config[NUM_SPDS] = {
45 [SPD800] = CORE_PLL_799,
46 [SPD1000] = CORE_PLL_1000,
47 [SPD1200] = CORE_PLL_1198,
48};
49
50s16 divn_val[16] = {
51 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
52};
53
54static struct pll_init_data tetris_pll_config[] = {
55 [SPD800] = TETRIS_PLL_799,
56 [SPD1000] = TETRIS_PLL_1000,
57 [SPD1200] = TETRIS_PLL_1198,
58 [SPD1350] = TETRIS_PLL_1352,
59 [SPD1400] = TETRIS_PLL_1401,
60};
61
62static struct pll_init_data pa_pll_config =
63 PASS_PLL_983;
64
65struct pll_init_data *get_pll_init_data(int pll)
66{
67 int speed;
68 struct pll_init_data *data;
69
70 switch (pll) {
71 case MAIN_PLL:
72 speed = get_max_dev_speed(speeds);
73 data = &core_pll_config[speed];
74 break;
75 case TETRIS_PLL:
76 speed = get_max_arm_speed(speeds);
77 data = &tetris_pll_config[speed];
78 break;
79 case PASS_PLL:
80 data = &pa_pll_config;
81 break;
82 default:
83 data = NULL;
84 }
85
86 return data;
87}
88
89#ifdef CONFIG_BOARD_EARLY_INIT_F
90int board_early_init_f(void)
91{
92 init_plls();
93
94 return 0;
95}
96#endif
97
98#if defined(CONFIG_MULTI_DTB_FIT)
99int board_fit_config_name_match(const char *name)
100{
101 if (!strcmp(name, "keystone-k2l-evm"))
102 return 0;
103
104 return -1;
105}
106#endif
107
108#ifdef CONFIG_SPL_BUILD
109void spl_init_keystone_plls(void)
110{
111 init_plls();
112}
113#endif
114