1
2
3
4
5menu "Multifunction device drivers"
6
7config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
16config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 default MISC
20 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
29 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
40 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
46config ALTERA_SYSID
47 bool "Altera Sysid support"
48 depends on MISC
49 help
50 Select this to enable a sysid for Altera devices. Please find
51 details on the "Embedded Peripherals IP User Guide" of Altera.
52
53config ATSHA204A
54 bool "Support for Atmel ATSHA204A module"
55 select BITREVERSE
56 depends on MISC
57 help
58 Enable support for I2C connected Atmel's ATSHA204A
59 CryptoAuthentication module found for example on the Turris Omnia
60 board.
61
62config GATEWORKS_SC
63 bool "Gateworks System Controller Support"
64 depends on MISC
65 help
66 Enable access for the Gateworks System Controller used on Gateworks
67 boards to provide a boot watchdog, power control, temperature monitor,
68 voltage ADCs, and EEPROM.
69
70config ROCKCHIP_EFUSE
71 bool "Rockchip e-fuse support"
72 depends on MISC
73 help
74 Enable (read-only) access for the e-fuse block found in Rockchip
75 SoCs: accesses can either be made using byte addressing and a length
76 or through child-nodes that are generated based on the e-fuse map
77 retrieved from the DTS.
78
79 This driver currently supports the RK3399 only, but can easily be
80 extended (by porting the read function from the Linux kernel sources)
81 to support other recent Rockchip devices.
82
83config ROCKCHIP_OTP
84 bool "Rockchip OTP Support"
85 depends on MISC
86 help
87 Enable (read-only) access for the one-time-programmable memory block
88 found in Rockchip SoCs: accesses can either be made using byte
89 addressing and a length or through child-nodes that are generated
90 based on the e-fuse map retrieved from the DTS.
91
92config SIFIVE_OTP
93 bool "SiFive eMemory OTP driver"
94 depends on MISC
95 help
96 Enable support for reading and writing the eMemory OTP on the
97 SiFive SoCs.
98
99config VEXPRESS_CONFIG
100 bool "Enable support for Arm Versatile Express config bus"
101 depends on MISC
102 help
103 If you say Y here, you will get support for accessing the
104 configuration bus on the Arm Versatile Express boards via
105 a sysreg driver.
106
107config CMD_CROS_EC
108 bool "Enable crosec command"
109 depends on CROS_EC
110 help
111 Enable command-line access to the Chrome OS EC (Embedded
112 Controller). This provides the 'crosec' command which has
113 a number of sub-commands for performing EC tasks such as
114 updating its flash, accessing a small saved context area
115 and talking to the I2C bus behind the EC (if there is one).
116
117config CROS_EC
118 bool "Enable Chrome OS EC"
119 help
120 Enable access to the Chrome OS EC. This is a separate
121 microcontroller typically available on a SPI bus on Chromebooks. It
122 provides access to the keyboard, some internal storage and may
123 control access to the battery and main PMIC depending on the
124 device. You can use the 'crosec' command to access it.
125
126config SPL_CROS_EC
127 bool "Enable Chrome OS EC in SPL"
128 depends on SPL
129 help
130 Enable access to the Chrome OS EC in SPL. This is a separate
131 microcontroller typically available on a SPI bus on Chromebooks. It
132 provides access to the keyboard, some internal storage and may
133 control access to the battery and main PMIC depending on the
134 device. You can use the 'crosec' command to access it.
135
136config TPL_CROS_EC
137 bool "Enable Chrome OS EC in TPL"
138 depends on TPL
139 help
140 Enable access to the Chrome OS EC in TPL. This is a separate
141 microcontroller typically available on a SPI bus on Chromebooks. It
142 provides access to the keyboard, some internal storage and may
143 control access to the battery and main PMIC depending on the
144 device. You can use the 'crosec' command to access it.
145
146config VPL_CROS_EC
147 bool "Enable Chrome OS EC in VPL"
148 depends on VPL
149 help
150 Enable access to the Chrome OS EC in VPL. This is a separate
151 microcontroller typically available on a SPI bus on Chromebooks. It
152 provides access to the keyboard, some internal storage and may
153 control access to the battery and main PMIC depending on the
154 device. You can use the 'crosec' command to access it.
155
156config CROS_EC_I2C
157 bool "Enable Chrome OS EC I2C driver"
158 depends on CROS_EC
159 help
160 Enable I2C access to the Chrome OS EC. This is used on older
161 ARM Chromebooks such as snow and spring before the standard bus
162 changed to SPI. The EC will accept commands across the I2C using
163 a special message protocol, and provide responses.
164
165config CROS_EC_LPC
166 bool "Enable Chrome OS EC LPC driver"
167 depends on CROS_EC
168 help
169 Enable I2C access to the Chrome OS EC. This is used on x86
170 Chromebooks such as link and falco. The keyboard is provided
171 through a legacy port interface, so on x86 machines the main
172 function of the EC is power and thermal management.
173
174config SPL_CROS_EC_LPC
175 bool "Enable Chrome OS EC LPC driver in SPL"
176 depends on CROS_EC
177 help
178 Enable I2C access to the Chrome OS EC. This is used on x86
179 Chromebooks such as link and falco. The keyboard is provided
180 through a legacy port interface, so on x86 machines the main
181 function of the EC is power and thermal management.
182
183config TPL_CROS_EC_LPC
184 bool "Enable Chrome OS EC LPC driver in TPL"
185 depends on CROS_EC
186 help
187 Enable I2C access to the Chrome OS EC. This is used on x86
188 Chromebooks such as link and falco. The keyboard is provided
189 through a legacy port interface, so on x86 machines the main
190 function of the EC is power and thermal management.
191
192config VPL_CROS_EC_LPC
193 bool "Enable Chrome OS EC LPC driver in VPL"
194 depends on CROS_EC
195 help
196 Enable I2C access to the Chrome OS EC. This is used on x86
197 Chromebooks such as link and falco. The keyboard is provided
198 through a legacy port interface, so on x86 machines the main
199 function of the EC is power and thermal management.
200
201config CROS_EC_SANDBOX
202 bool "Enable Chrome OS EC sandbox driver"
203 depends on CROS_EC && SANDBOX
204 help
205 Enable a sandbox emulation of the Chrome OS EC. This supports
206 keyboard (use the -l flag to enable the LCD), verified boot context,
207 EC flash read/write/erase support and a few other things. It is
208 enough to perform a Chrome OS verified boot on sandbox.
209
210config SPL_CROS_EC_SANDBOX
211 bool "Enable Chrome OS EC sandbox driver in SPL"
212 depends on SPL_CROS_EC && SANDBOX
213 help
214 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
215 keyboard (use the -l flag to enable the LCD), verified boot context,
216 EC flash read/write/erase support and a few other things. It is
217 enough to perform a Chrome OS verified boot on sandbox.
218
219config TPL_CROS_EC_SANDBOX
220 bool "Enable Chrome OS EC sandbox driver in TPL"
221 depends on TPL_CROS_EC && SANDBOX
222 help
223 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
224 keyboard (use the -l flag to enable the LCD), verified boot context,
225 EC flash read/write/erase support and a few other things. It is
226 enough to perform a Chrome OS verified boot on sandbox.
227
228config VPL_CROS_EC_SANDBOX
229 bool "Enable Chrome OS EC sandbox driver in VPL"
230 depends on VPL_CROS_EC && SANDBOX
231 help
232 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
233 keyboard (use the -l flag to enable the LCD), verified boot context,
234 EC flash read/write/erase support and a few other things. It is
235 enough to perform a Chrome OS verified boot on sandbox.
236
237config CROS_EC_SPI
238 bool "Enable Chrome OS EC SPI driver"
239 depends on CROS_EC
240 help
241 Enable SPI access to the Chrome OS EC. This is used on newer
242 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
243 provides a faster and more robust interface than I2C but the bugs
244 are less interesting.
245
246config DS4510
247 bool "Enable support for DS4510 CPU supervisor"
248 help
249 Enable support for the Maxim DS4510 CPU supervisor. It has an
250 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
251 and a configurable timer for the supervisor function. The device is
252 connected over I2C.
253
254config FSL_SEC_MON
255 bool "Enable FSL SEC_MON Driver"
256 help
257 Freescale Security Monitor block is responsible for monitoring
258 system states.
259 Security Monitor can be transitioned on any security failures,
260 like software violations or hardware security violations.
261
262config IRQ
263 bool "Interrupt controller"
264 help
265 This enables support for interrupt controllers, including ITSS.
266 Some devices have extra features, such as Apollo Lake. The
267 device has its own uclass since there are several operations
268 involved.
269
270config JZ4780_EFUSE
271 bool "Ingenic JZ4780 eFUSE support"
272 depends on ARCH_JZ47XX
273 help
274 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
275
276config MXC_OCOTP
277 bool "Enable MXC OCOTP Driver"
278 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
279 default y
280 help
281 If you say Y here, you will get support for the One Time
282 Programmable memory pages that are stored on the some
283 Freescale i.MX processors.
284
285config SPL_MXC_OCOTP
286 bool "Enable MXC OCOTP driver in SPL"
287 depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
288 default y
289 help
290 If you say Y here, you will get support for the One Time
291 Programmable memory pages, that are stored on some
292 Freescale i.MX processors, in SPL.
293
294config NUVOTON_NCT6102D
295 bool "Enable Nuvoton NCT6102D Super I/O driver"
296 help
297 If you say Y here, you will get support for the Nuvoton
298 NCT6102D Super I/O driver. This can be used to enable or
299 disable the legacy UART, the watchdog or other devices
300 in the Nuvoton Super IO chips on X86 platforms.
301
302config P2SB
303 bool "Intel Primary to Sideband Bridge"
304 depends on X86 || SANDBOX
305 help
306 This enables support for the Intel Primary to Sideband Bridge,
307 abbreviated to P2SB. The P2SB is used to access various peripherals
308 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
309 space. The space is segmented into different channels and peripherals
310 are accessed by device-specific means within those channels. Devices
311 should be added in the device tree as subnodes of the P2SB. A
312 Peripheral Channel Register? (PCR) API is provided to access those
313 devices - see pcr_readl(), etc.
314
315config SPL_P2SB
316 bool "Intel Primary to Sideband Bridge in SPL"
317 depends on SPL && (X86 || SANDBOX)
318 help
319 The Primary to Sideband Bridge is used to access various peripherals
320 through memory-mapped I/O in a large chunk of PCI space. The space is
321 segmented into different channels and peripherals are accessed by
322 device-specific means within those channels. Devices should be added
323 in the device tree as subnodes of the p2sb.
324
325config TPL_P2SB
326 bool "Intel Primary to Sideband Bridge in TPL"
327 depends on TPL && (X86 || SANDBOX)
328 help
329 The Primary to Sideband Bridge is used to access various peripherals
330 through memory-mapped I/O in a large chunk of PCI space. The space is
331 segmented into different channels and peripherals are accessed by
332 device-specific means within those channels. Devices should be added
333 in the device tree as subnodes of the p2sb.
334
335config PWRSEQ
336 bool "Enable power-sequencing drivers"
337 depends on DM
338 help
339 Power-sequencing drivers provide support for controlling power for
340 devices. They are typically referenced by a phandle from another
341 device. When the device is started up, its power sequence can be
342 initiated.
343
344config SPL_PWRSEQ
345 bool "Enable power-sequencing drivers for SPL"
346 depends on PWRSEQ
347 help
348 Power-sequencing drivers provide support for controlling power for
349 devices. They are typically referenced by a phandle from another
350 device. When the device is started up, its power sequence can be
351 initiated.
352
353config PCA9551_LED
354 bool "Enable PCA9551 LED driver"
355 help
356 Enable driver for PCA9551 LED controller. This controller
357 is connected via I2C. So I2C needs to be enabled.
358
359config PCA9551_I2C_ADDR
360 hex "I2C address of PCA9551 LED controller"
361 depends on PCA9551_LED
362 default 0x60
363 help
364 The I2C address of the PCA9551 LED controller.
365
366config STM32MP_FUSE
367 bool "Enable STM32MP fuse wrapper providing the fuse API"
368 depends on ARCH_STM32MP && MISC
369 default y if CMD_FUSE
370 help
371 If you say Y here, you will get support for the fuse API (OTP)
372 for STM32MP architecture.
373 This API is needed for CMD_FUSE.
374
375config STM32_RCC
376 bool "Enable RCC driver for the STM32 SoC's family"
377 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
378 help
379 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
380 block) is responsible of the management of the clock and reset
381 generation.
382 This driver is similar to an MFD driver in the Linux kernel.
383
384config TEGRA_CAR
385 bool "Enable support for the Tegra CAR driver"
386 depends on TEGRA_NO_BPMP
387 help
388 The Tegra CAR (Clock and Reset Controller) is a HW module that
389 controls almost all clocks and resets in a Tegra SoC.
390
391config TEGRA186_BPMP
392 bool "Enable support for the Tegra186 BPMP driver"
393 depends on TEGRA186
394 help
395 The Tegra BPMP (Boot and Power Management Processor) is a separate
396 auxiliary CPU embedded into Tegra to perform power management work,
397 and controls related features such as clocks, resets, power domains,
398 PMIC I2C bus, etc. This driver provides the core low-level
399 communication path by which feature-specific drivers (such as clock)
400 can make requests to the BPMP. This driver is similar to an MFD
401 driver in the Linux kernel.
402
403config TEST_DRV
404 bool "Enable support for test drivers"
405 default y if SANDBOX
406 help
407 This enables drivers and uclasses that provides a way of testing the
408 operations of memory allocation and driver/uclass methods in driver
409 model. This should only be enabled for testing as it is not useful for
410 anything else.
411
412config USB_HUB_USB251XB
413 tristate "USB251XB Hub Controller Configuration Driver"
414 depends on I2C
415 help
416 This option enables support for configuration via SMBus of the
417 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
418 parameters may be set in devicetree or platform data.
419 Say Y or M here if you need to configure such a device via SMBus.
420
421config TWL4030_LED
422 bool "Enable TWL4030 LED controller"
423 help
424 Enable this to add support for the TWL4030 LED controller.
425
426config WINBOND_W83627
427 bool "Enable Winbond Super I/O driver"
428 help
429 If you say Y here, you will get support for the Winbond
430 W83627 Super I/O driver. This can be used to enable the
431 legacy UART or other devices in the Winbond Super IO chips
432 on X86 platforms.
433
434config QFW
435 bool
436 help
437 Hidden option to enable QEMU fw_cfg interface and uclass. This will
438 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
439
440config QFW_PIO
441 bool
442 depends on QFW
443 help
444 Hidden option to enable PIO QEMU fw_cfg interface. This will be
445 selected by the appropriate QEMU board.
446
447config QFW_MMIO
448 bool
449 depends on QFW
450 help
451 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
452 selected by the appropriate QEMU board.
453
454config I2C_EEPROM
455 bool "Enable driver for generic I2C-attached EEPROMs"
456 depends on MISC
457 help
458 Enable a generic driver for EEPROMs attached via I2C.
459
460
461config SPL_I2C_EEPROM
462 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
463 depends on MISC && SPL && SPL_DM
464 help
465 This option is an SPL-variant of the I2C_EEPROM option.
466 See the help of I2C_EEPROM for details.
467
468config SYS_I2C_EEPROM_ADDR
469 hex "Chip address of the EEPROM device"
470 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
471 default 0
472
473if I2C_EEPROM
474
475config SYS_I2C_EEPROM_ADDR_OVERFLOW
476 hex "EEPROM Address Overflow"
477 default 0x0
478 help
479 EEPROM chips that implement "address overflow" are ones
480 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
481 address and the extra bits end up in the "chip address" bit
482 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
483 byte chips.
484
485endif
486
487config GDSYS_RXAUI_CTRL
488 bool "Enable gdsys RXAUI control driver"
489 depends on MISC
490 help
491 Support gdsys FPGA's RXAUI control.
492
493config GDSYS_IOEP
494 bool "Enable gdsys IOEP driver"
495 depends on MISC
496 help
497 Support gdsys FPGA's IO endpoint driver.
498
499config MPC83XX_SERDES
500 bool "Enable MPC83xx serdes driver"
501 depends on MISC
502 help
503 Support for serdes found on MPC83xx SoCs.
504
505config FS_LOADER
506 bool "Enable loader driver for file system"
507 help
508 This is file system generic loader which can be used to load
509 the file image from the storage into target such as memory.
510
511 The consumer driver would then use this loader to program whatever,
512 ie. the FPGA device.
513
514config SPL_FS_LOADER
515 bool "Enable loader driver for file system"
516 help
517 This is file system generic loader which can be used to load
518 the file image from the storage into target such as memory.
519
520 The consumer driver would then use this loader to program whatever,
521 ie. the FPGA device.
522
523config GDSYS_SOC
524 bool "Enable gdsys SOC driver"
525 depends on MISC
526 help
527 Support for gdsys IHS SOC, a simple bus associated with each gdsys
528 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
529 register maps are contained within the FPGA's register map.
530
531config IHS_FPGA
532 bool "Enable IHS FPGA driver"
533 depends on MISC
534 help
535 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
536 gdsys devices, which supply the majority of the functionality offered
537 by the devices. This driver supports both CON and CPU variants of the
538 devices, depending on the device tree entry.
539config ESM_K3
540 bool "Enable K3 ESM driver"
541 depends on ARCH_K3
542 help
543 Support ESM (Error Signaling Module) on TI K3 SoCs.
544
545config MICROCHIP_FLEXCOM
546 bool "Enable Microchip Flexcom driver"
547 depends on MISC
548 help
549 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
550 an I2C controller and an USART.
551 Only one function can be used at a time and is chosen at boot time
552 according to the device tree.
553
554config K3_AVS0
555 depends on ARCH_K3 && SPL_DM_REGULATOR
556 bool "AVS class 0 support for K3 devices"
557 help
558 K3 devices have the optimized voltage values for the main voltage
559 domains stored in efuse within the VTM IP. This driver reads the
560 optimized voltage from the efuse, so that it can be programmed
561 to the PMIC on board.
562
563config ESM_PMIC
564 bool "Enable PMIC ESM driver"
565 depends on DM_PMIC
566 help
567 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
568 typically to reboot the board in error condition.
569
570config FSL_IFC
571 bool
572
573config SL28CPLD
574 bool "Enable Kontron sl28cpld multi-function driver"
575 depends on DM_I2C
576 help
577 Support for the Kontron sl28cpld management controller. This is
578 the base driver which provides common access methods for the
579 sub-drivers.
580
581endmenu
582
