1
2menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
4if MTD_RAW_NAND
5
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
12config SPL_SYS_NAND_SELF_INIT
13 bool
14 depends on !SPL_NAND_SIMPLE
15 help
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
18
19config TPL_SYS_NAND_SELF_INIT
20 bool
21 depends on TPL_NAND_SUPPORT
22 help
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
25
26config SYS_NAND_DRIVER_ECC_LAYOUT
27 bool "Omit standard ECC layouts to save space"
28 help
29 Omit standard ECC layouts to save space. Select this if your driver
30 is known to provide its own ECC layout.
31
32config SYS_NAND_USE_FLASH_BBT
33 bool "Enable BBT (Bad Block Table) support"
34 help
35 Enable the BBT (Bad Block Table) usage.
36
37config NAND_ATMEL
38 bool "Support Atmel NAND controller"
39 select SYS_NAND_SELF_INIT
40 imply SYS_NAND_USE_FLASH_BBT
41 help
42 Enable this driver for NAND flash platforms using an Atmel NAND
43 controller.
44
45if NAND_ATMEL
46
47config ATMEL_NAND_HWECC
48 bool "Atmel Hardware ECC"
49
50config ATMEL_NAND_HW_PMECC
51 bool "Atmel Programmable Multibit ECC (PMECC)"
52 select ATMEL_NAND_HWECC
53 help
54 The Programmable Multibit ECC (PMECC) controller is a programmable
55 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
56
57config PMECC_CAP
58 int "PMECC Correctable ECC Bits"
59 depends on ATMEL_NAND_HW_PMECC
60 default 2
61 help
62 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
63
64config PMECC_SECTOR_SIZE
65 int "PMECC Sector Size"
66 depends on ATMEL_NAND_HW_PMECC
67 default 512
68 help
69 Sector size, in bytes, can be 512 or 1024.
70
71config SPL_GENERATE_ATMEL_PMECC_HEADER
72 bool "Atmel PMECC Header Generation"
73 select ATMEL_NAND_HWECC
74 select ATMEL_NAND_HW_PMECC
75 help
76 Generate Programmable Multibit ECC (PMECC) header for SPL image.
77
78endif
79
80config NAND_BRCMNAND
81 bool "Support Broadcom NAND controller"
82 depends on OF_CONTROL && DM && DM_MTD
83 select SYS_NAND_SELF_INIT
84 help
85 Enable the driver for NAND flash on platforms using a Broadcom NAND
86 controller.
87
88config NAND_BRCMNAND_6368
89 bool "Support Broadcom NAND controller on bcm6368"
90 depends on NAND_BRCMNAND && ARCH_BMIPS
91 help
92 Enable support for broadcom nand driver on bcm6368.
93
94config NAND_BRCMNAND_6753
95 bool "Support Broadcom NAND controller on bcm6753"
96 depends on NAND_BRCMNAND && ARCH_BCM6753
97 help
98 Enable support for broadcom nand driver on bcm6753.
99
100config NAND_BRCMNAND_68360
101 bool "Support Broadcom NAND controller on bcm68360"
102 depends on NAND_BRCMNAND && ARCH_BCM68360
103 help
104 Enable support for broadcom nand driver on bcm68360.
105
106config NAND_BRCMNAND_6838
107 bool "Support Broadcom NAND controller on bcm6838"
108 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
109 help
110 Enable support for broadcom nand driver on bcm6838.
111
112config NAND_BRCMNAND_6858
113 bool "Support Broadcom NAND controller on bcm6858"
114 depends on NAND_BRCMNAND && ARCH_BCM6858
115 help
116 Enable support for broadcom nand driver on bcm6858.
117
118config NAND_BRCMNAND_63158
119 bool "Support Broadcom NAND controller on bcm63158"
120 depends on NAND_BRCMNAND && ARCH_BCM63158
121 help
122 Enable support for broadcom nand driver on bcm63158.
123
124config NAND_DAVINCI
125 bool "Support TI Davinci NAND controller"
126 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
127 help
128 Enable this driver for NAND flash controllers available in TI Davinci
129 and Keystone2 platforms
130
131config KEYSTONE_RBL_NAND
132 depends on ARCH_KEYSTONE
133 def_bool y
134
135config SPL_NAND_LOAD
136 def_bool y
137 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
138
139config NAND_DENALI
140 bool
141 select SYS_NAND_SELF_INIT
142 imply CMD_NAND
143
144config NAND_DENALI_DT
145 bool "Support Denali NAND controller as a DT device"
146 select NAND_DENALI
147 depends on OF_CONTROL && DM_MTD
148 help
149 Enable the driver for NAND flash on platforms using a Denali NAND
150 controller as a DT device.
151
152config NAND_FSL_ELBC
153 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
154 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
155 select SPL_SYS_NAND_SELF_INIT
156 select SYS_NAND_SELF_INIT
157 depends on FSL_ELBC
158 help
159 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
160
161config NAND_FSL_ELBC_DT
162 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
163 depends on NAND_FSL_ELBC
164
165config NAND_FSL_IFC
166 bool "Support Freescale Integrated Flash Controller NAND driver"
167 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
168 select SPL_SYS_NAND_SELF_INIT
169 select SYS_NAND_SELF_INIT
170 select FSL_IFC
171 help
172 Enable the Freescale Integrated Flash Controller NAND driver.
173
174config NAND_LPC32XX_MLC
175 bool "Support LPC32XX_MLC controller"
176 select SYS_NAND_SELF_INIT
177 help
178 Enable the LPC32XX MLC NAND controller.
179
180config NAND_LPC32XX_SLC
181 bool "Support LPC32XX_SLC controller"
182 help
183 Enable the LPC32XX SLC NAND controller.
184
185config NAND_OMAP_GPMC
186 bool "Support OMAP GPMC NAND controller"
187 depends on ARCH_OMAP2PLUS
188 help
189 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
190 GPMC controller is used for parallel NAND flash devices, and can
191 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
192 and BCH16 ECC algorithms.
193
194if NAND_OMAP_GPMC
195
196config NAND_OMAP_GPMC_PREFETCH
197 bool "Enable GPMC Prefetch"
198 default y
199 help
200 On OMAP platforms that use the GPMC controller
201 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
202 uses the prefetch mode to speed up read operations.
203
204config NAND_OMAP_ELM
205 bool "Enable ELM driver for OMAPxx and AMxx platforms."
206 depends on !OMAP34XX
207 help
208 ELM controller is used for ECC error detection (not ECC calculation)
209 of BCH4, BCH8 and BCH16 ECC algorithms.
210 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
211 thus such SoC platforms need to depend on software library for ECC error
212 detection. However ECC calculation on such plaforms would still be
213 done by GPMC controller.
214
215choice
216 prompt "ECC scheme"
217 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
218 help
219 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
220 It can take following values:
221 OMAP_ECC_HAM1_CODE_SW
222 1-bit Hamming code using software lib.
223 (for legacy devices only)
224 OMAP_ECC_HAM1_CODE_HW
225 1-bit Hamming code using GPMC hardware.
226 (for legacy devices only)
227 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
228 4-bit BCH code (unsupported)
229 OMAP_ECC_BCH4_CODE_HW
230 4-bit BCH code (unsupported)
231 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
232 8-bit BCH code with
233 - ecc calculation using GPMC hardware engine,
234 - error detection using software library.
235 - requires CONFIG_BCH to enable software BCH library
236 (For legacy device which do not have ELM h/w engine)
237 OMAP_ECC_BCH8_CODE_HW
238 8-bit BCH code with
239 - ecc calculation using GPMC hardware engine,
240 - error detection using ELM hardware engine.
241 OMAP_ECC_BCH16_CODE_HW
242 16-bit BCH code with
243 - ecc calculation using GPMC hardware engine,
244 - error detection using ELM hardware engine.
245
246 How to select ECC scheme on OMAP and AMxx platforms ?
247 -----------------------------------------------------
248 Though higher ECC schemes have more capability to detect and correct
249 bit-flips, but still selection of ECC scheme is dependent on following
250 - hardware engines present in SoC.
251 Some legacy OMAP SoC do not have ELM h/w engine thus such
252 SoC cannot support BCHx_HW ECC schemes.
253 - size of OOB/Spare region
254 With higher ECC schemes, more OOB/Spare area is required to
255 store ECC. So choice of ECC scheme is limited by NAND oobsize.
256
257 In general following expression can help:
258 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
259 where
260 NAND_OOBSIZE = number of bytes available in
261 OOB/spare area per NAND page.
262 NAND_PAGESIZE = bytes in main-area of NAND page.
263 ECC_BYTES = number of ECC bytes generated to
264 protect 512 bytes of data, which is:
265 3 for HAM1_xx ecc schemes
266 7 for BCH4_xx ecc schemes
267 14 for BCH8_xx ecc schemes
268 26 for BCH16_xx ecc schemes
269
270 example to check for BCH16 on 2K page NAND
271 NAND_PAGESIZE = 2048
272 NAND_OOBSIZE = 64
273 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
274 Thus BCH16 cannot be supported on 2K page NAND.
275
276 However, for 4K pagesize NAND
277 NAND_PAGESIZE = 4096
278 NAND_OOBSIZE = 224
279 ECC_BYTES = 26
280 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
281 Thus BCH16 can be supported on 4K page NAND.
282
283config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
284 bool "1-bit Hamming code using software lib"
285
286config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
287 bool "1-bit Hamming code using GPMC hardware"
288
289config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
290 bool "8-bit BCH code with HW calculation SW error detection"
291
292config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
293 bool "8-bit BCH code with HW calculation and error detection"
294
295config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
296 bool "16-bit BCH code with HW calculation and error detection"
297
298endchoice
299
300config NAND_OMAP_ECCSCHEME
301 int
302 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
303 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
304 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
305 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
306 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
307 help
308 This must be kept in sync with the enum in
309 include/linux/mtd/omap_gpmc.h
310
311endif
312
313config NAND_VF610_NFC
314 bool "Support for Freescale NFC for VF610"
315 select SYS_NAND_SELF_INIT
316 select SYS_NAND_DRIVER_ECC_LAYOUT
317 imply CMD_NAND
318 help
319 Enables support for NAND Flash Controller on some Freescale
320 processors like the VF610, MCF54418 or Kinetis K70.
321 The driver supports a maximum 2k page size. The driver
322 currently does not support hardware ECC.
323
324if NAND_VF610_NFC
325
326config NAND_VF610_NFC_DT
327 bool "Support Vybrid's vf610 NAND controller as a DT device"
328 depends on OF_CONTROL && DM_MTD
329 help
330 Enable the driver for Vybrid's vf610 NAND flash on platforms
331 using device tree.
332
333choice
334 prompt "Hardware ECC strength"
335 depends on NAND_VF610_NFC
336 default SYS_NAND_VF610_NFC_45_ECC_BYTES
337 help
338 Select the ECC strength used in the hardware BCH ECC block.
339
340config SYS_NAND_VF610_NFC_45_ECC_BYTES
341 bool "24-error correction (45 ECC bytes)"
342
343config SYS_NAND_VF610_NFC_60_ECC_BYTES
344 bool "32-error correction (60 ECC bytes)"
345
346endchoice
347
348endif
349
350config NAND_PXA3XX
351 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
352 select SYS_NAND_SELF_INIT
353 select DM_MTD
354 select REGMAP
355 select SYSCON
356 imply CMD_NAND
357 help
358 This enables the driver for the NAND flash device found on
359 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
360
361config NAND_SUNXI
362 bool "Support for NAND on Allwinner SoCs"
363 default ARCH_SUNXI
364 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
365 select SYS_NAND_SELF_INIT
366 select SYS_NAND_U_BOOT_LOCATIONS
367 select SPL_NAND_SUPPORT
368 select SPL_SYS_NAND_SELF_INIT
369 imply CMD_NAND
370 ---help---
371 Enable support for NAND. This option enables the standard and
372 SPL drivers.
373 The SPL driver only supports reading from the NAND using DMA
374 transfers.
375
376if NAND_SUNXI
377
378config NAND_SUNXI_SPL_ECC_STRENGTH
379 int "Allwinner NAND SPL ECC Strength"
380 default 64
381
382config NAND_SUNXI_SPL_ECC_SIZE
383 int "Allwinner NAND SPL ECC Step Size"
384 default 1024
385
386config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
387 int "Allwinner NAND SPL Usable Page Size"
388 default 1024
389
390endif
391
392config NAND_ARASAN
393 bool "Configure Arasan Nand"
394 select SYS_NAND_SELF_INIT
395 depends on DM_MTD
396 imply CMD_NAND
397 help
398 This enables Nand driver support for Arasan nand flash
399 controller. This uses the hardware ECC for read and
400 write operations.
401
402config NAND_MXC
403 bool "MXC NAND support"
404 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
405 imply CMD_NAND
406 help
407 This enables the NAND driver for the NAND flash controller on the
408 i.MX27 / i.MX31 / i.MX5 processors.
409
410config NAND_MXS
411 bool "MXS NAND support"
412 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
413 select SPL_SYS_NAND_SELF_INIT
414 select SYS_NAND_SELF_INIT
415 imply CMD_NAND
416 select APBH_DMA
417 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
418 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
419 help
420 This enables NAND driver for the NAND flash controller on the
421 MXS processors.
422
423if NAND_MXS
424
425config NAND_MXS_DT
426 bool "Support MXS NAND controller as a DT device"
427 depends on OF_CONTROL && DM_MTD
428 help
429 Enable the driver for MXS NAND flash on platforms using
430 device tree.
431
432config NAND_MXS_USE_MINIMUM_ECC
433 bool "Use minimum ECC strength supported by the controller"
434 default false
435
436endif
437
438config NAND_MXIC
439 bool "Macronix raw NAND controller"
440 select SYS_NAND_SELF_INIT
441 help
442 This selects the Macronix raw NAND controller driver.
443
444config NAND_ZYNQ
445 bool "Support for Zynq Nand controller"
446 select SPL_SYS_NAND_SELF_INIT
447 select SYS_NAND_SELF_INIT
448 select DM_MTD
449 imply CMD_NAND
450 help
451 This enables Nand driver support for Nand flash controller
452 found on Zynq SoC.
453
454config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
455 bool "Enable use of 1st stage bootloader timing for NAND"
456 depends on NAND_ZYNQ
457 help
458 This flag prevent U-boot reconfigure NAND flash controller and reuse
459 the NAND timing from 1st stage bootloader.
460
461config NAND_OCTEONTX
462 bool "Support for OcteonTX NAND controller"
463 select SYS_NAND_SELF_INIT
464 imply CMD_NAND
465 help
466 This enables Nand flash controller hardware found on the OcteonTX
467 processors.
468
469config NAND_OCTEONTX_HW_ECC
470 bool "Support Hardware ECC for OcteonTX NAND controller"
471 depends on NAND_OCTEONTX
472 default y
473 help
474 This enables Hardware BCH engine found on the OcteonTX processors to
475 support ECC for NAND flash controller.
476
477config NAND_STM32_FMC2
478 bool "Support for NAND controller on STM32MP SoCs"
479 depends on ARCH_STM32MP
480 select SYS_NAND_SELF_INIT
481 imply CMD_NAND
482 help
483 Enables support for NAND Flash chips on SoCs containing the FMC2
484 NAND controller. This controller is found on STM32MP SoCs.
485 The controller supports a maximum 8k page size and supports
486 a maximum 8-bit correction error per sector of 512 bytes.
487
488config CORTINA_NAND
489 bool "Support for NAND controller on Cortina-Access SoCs"
490 depends on CORTINA_PLATFORM
491 select SYS_NAND_SELF_INIT
492 select DM_MTD
493 imply CMD_NAND
494 help
495 Enables support for NAND Flash chips on Coartina-Access SoCs platform
496 This controller is found on Presidio/Venus SoCs.
497 The controller supports a maximum 8k page size and supports
498 a maximum 40-bit error correction per sector of 1024 bytes.
499
500config ROCKCHIP_NAND
501 bool "Support for NAND controller on Rockchip SoCs"
502 depends on ARCH_ROCKCHIP
503 select SYS_NAND_SELF_INIT
504 select DM_MTD
505 imply CMD_NAND
506 help
507 Enables support for NAND Flash chips on Rockchip SoCs platform.
508 This controller is found on Rockchip SoCs.
509 There are four different versions of NAND FLASH Controllers,
510 including:
511 NFC v600: RK2928, RK3066, RK3188
512 NFC v622: RK3036, RK3128
513 NFC v800: RK3308, RV1108
514 NFC v900: PX30, RK3326
515
516config TEGRA_NAND
517 bool "Support for NAND controller on Tegra SoCs"
518 depends on ARCH_TEGRA
519 select SYS_NAND_SELF_INIT
520 imply CMD_NAND
521 help
522 Enables support for NAND Flash chips on Tegra SoCs platforms.
523
524comment "Generic NAND options"
525
526config SYS_NAND_BLOCK_SIZE
527 hex "NAND chip eraseblock size"
528 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
529 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
530 help
531 Number of data bytes in one eraseblock for the NAND chip on the
532 board. This is the multiple of NAND_PAGE_SIZE and the number of
533 pages.
534
535config SYS_NAND_ONFI_DETECTION
536 bool "Enable detection of ONFI compliant devices during probe"
537 help
538 Enables detection of ONFI compliant devices during probe.
539 And fetching device parameters flashed on device, by parsing
540 ONFI parameter page.
541
542config SYS_NAND_PAGE_COUNT
543 hex "NAND chip page count"
544 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
545 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
546 help
547 Number of pages in the NAND chip.
548
549config SYS_NAND_PAGE_SIZE
550 hex "NAND chip page size"
551 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
552 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
553 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
554 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
555 help
556 Number of data bytes in one page for the NAND chip on the
557 board, not including the OOB area.
558
559config SYS_NAND_OOBSIZE
560 hex "NAND chip OOB size"
561 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
562 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
563 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
564 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
565 help
566 Number of bytes in the Out-Of-Band area for the NAND chip on
567 the board.
568
569
570
571config SYS_NAND_BUSWIDTH_16BIT
572 bool "Use 16-bit NAND interface"
573 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
574 help
575 Indicates that NAND device has 16-bit wide data-bus. In absence of this
576 config, bus-width of NAND device is assumed to be either 8-bit and later
577 determined by reading ONFI params.
578 Above config is useful when NAND device's bus-width information cannot
579 be determined from on-chip ONFI params, like in following scenarios:
580 - SPL boot does not support reading of ONFI parameters. This is done to
581 keep SPL code foot-print small.
582 - In current U-Boot flow using nand_init(), driver initialization
583 happens in board_nand_init() which is called before any device probe
584 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
585 not available while configuring controller. So a static CONFIG_NAND_xx
586 is needed to know the device's bus-width in advance.
587
588if SPL
589
590config SYS_NAND_5_ADDR_CYCLE
591 bool "Wait 5 address cycles during NAND commands"
592 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
593 (SPL_NAND_SUPPORT && NAND_ATMEL)
594 default y
595 help
596 Some controllers require waiting for 5 address cycles when issuing
597 some commands, on NAND chips larger than 128MiB.
598
599choice
600 prompt "NAND bad block marker/indicator position in the OOB"
601 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
602 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
603 default HAS_NAND_LARGE_BADBLOCK_POS
604 help
605 In the OOB, which position contains the badblock information.
606
607config HAS_NAND_LARGE_BADBLOCK_POS
608 bool "Set the bad block marker/indicator to the 'large' position"
609
610config HAS_NAND_SMALL_BADBLOCK_POS
611 bool "Set the bad block marker/indicator to the 'small' position"
612
613endchoice
614
615config SYS_NAND_BAD_BLOCK_POS
616 int
617 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
618 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
619
620config SYS_NAND_U_BOOT_LOCATIONS
621 bool "Define U-boot binaries locations in NAND"
622 help
623 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
624 This option should not be enabled when compiling U-boot for boards
625 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
626 file.
627
628config SYS_NAND_U_BOOT_OFFS
629 hex "Location in NAND to read U-Boot from"
630 default 0x800000 if NAND_SUNXI
631 depends on SYS_NAND_U_BOOT_LOCATIONS
632 help
633 Set the offset from the start of the nand where u-boot should be
634 loaded from.
635
636config SYS_NAND_U_BOOT_OFFS_REDUND
637 hex "Location in NAND to read U-Boot from"
638 default SYS_NAND_U_BOOT_OFFS
639 depends on SYS_NAND_U_BOOT_LOCATIONS
640 help
641 Set the offset from the start of the nand where the redundant u-boot
642 should be loaded from.
643
644config SPL_NAND_AM33XX_BCH
645 bool "Enables SPL-NAND driver which supports ELM based"
646 depends on NAND_OMAP_GPMC && !OMAP34XX
647 default y
648 help
649 Hardware ECC correction. This is useful for platforms which have ELM
650 hardware engine and use NAND boot mode.
651 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
652 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
653 SPL-NAND driver with software ECC correction support.
654
655config SPL_NAND_DENALI
656 bool "Support Denali NAND controller for SPL"
657 help
658 This is a small implementation of the Denali NAND controller
659 for use on SPL.
660
661config NAND_DENALI_SPARE_AREA_SKIP_BYTES
662 int "Number of bytes skipped in OOB area"
663 depends on SPL_NAND_DENALI
664 range 0 63
665 help
666 This option specifies the number of bytes to skip from the beginning
667 of OOB area before last ECC sector data starts. This is potentially
668 used to preserve the bad block marker in the OOB area.
669
670config SPL_NAND_SIMPLE
671 bool "Use simple SPL NAND driver"
672 depends on !SPL_NAND_AM33XX_BCH
673 help
674 Support for NAND boot using simple NAND drivers that
675 expose the cmd_ctrl() interface.
676endif
677
678endif
679
