LXR uboot/drivers/mtd/nand/raw/octeontx

   1/* SPDX-License-Identifier:    GPL-2.0
   2 *
   3 * Copyright (C) 2018 Marvell International Ltd.
   4 */
   5
   6#ifndef __OCTEONTX_BCH_H__
   7#define __OCTEONTX_BCH_H__
   8
   9#include "octeontx_bch_regs.h"
  10
  11/* flags to indicate the features supported */
  12#define BCH_FLAG_SRIOV_ENABLED          BIT(1)
  13
  14/*
  15 * BCH Registers map for 81xx
  16 */
  17
  18/* PF registers */
  19#define BCH_CTL                         0x0ull
  20#define BCH_ERR_CFG                     0x10ull
  21#define BCH_BIST_RESULT                 0x80ull
  22#define BCH_ERR_INT                     0x88ull
  23#define BCH_ERR_INT_W1S                 0x90ull
  24#define BCH_ERR_INT_ENA_W1C             0xA0ull
  25#define BCH_ERR_INT_ENA_W1S             0xA8ull
  26
  27/* VF registers */
  28#define BCH_VQX_CTL(z)                  0x0ull
  29#define BCH_VQX_CMD_BUF(z)              0x8ull
  30#define BCH_VQX_CMD_PTR(z)              0x20ull
  31#define BCH_VQX_DOORBELL(z)             0x800ull
  32
  33#define BCHPF_DRIVER_NAME       "octeontx-bchpf"
  34#define BCHVF_DRIVER_NAME       "octeontx-bchvf"
  35
  36struct bch_device {
  37        struct list_head list;
  38        u8 max_vfs;
  39        u8 vfs_enabled;
  40        u8 vfs_in_use;
  41        u32 flags;
  42        void __iomem *reg_base;
  43        struct udevice *dev;
  44};
  45
  46struct bch_vf {
  47        u16 flags;
  48        u8 vfid;
  49        u8 node;
  50        u8 priority;
  51        struct udevice *dev;
  52        void __iomem *reg_base;
  53};
  54
  55struct buf_ptr {
  56        u8 *vptr;
  57        dma_addr_t dma_addr;
  58        u16 size;
  59};
  60
  61void *octeontx_bch_getv(void);
  62void octeontx_bch_putv(void *token);
  63void *octeontx_bch_getp(void);
  64void octeontx_bch_putp(void *token);
  65int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp,
  66                      dma_addr_t handle);
  67/**
  68 * Given a data block calculate the ecc data and fill in the response
  69 *
  70 * @param[in] block     8-byte aligned pointer to data block to calculate ECC
  71 * @param block_size    Size of block in bytes, must be a multiple of two.
  72 * @param bch_level     Number of errors that must be corrected.  The number of
  73 *                      parity bytes is equal to ((15 * bch_level) + 7) / 8.
  74 *                      Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
  75 * @param[out] ecc      8-byte aligned pointer to where ecc data should go
  76 * @param[in] resp      pointer to where responses will be written.
  77 *
  78 * Return: Zero on success, negative on failure.
  79 */
  80int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size,
  81                        u8 bch_level, dma_addr_t ecc, dma_addr_t resp);
  82
  83/**
  84 * Given a data block and ecc data correct the data block
  85 *
  86 * @param[in] block_ecc_in      8-byte aligned pointer to data block with ECC
  87 *                              data concatenated to the end to correct
  88 * @param block_size            Size of block in bytes, must be a multiple of
  89 *                              two.
  90 * @param bch_level             Number of errors that must be corrected.  The
  91 *                              number of parity bytes is equal to
  92 *                              ((15 * bch_level) + 7) / 8.
  93 *                              Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64.
  94 * @param[out] block_out        8-byte aligned pointer to corrected data buffer.
  95 *                              This should not be the same as block_ecc_in.
  96 * @param[in] resp              pointer to where responses will be written.
  97 *
  98 * Return: Zero on success, negative on failure.
  99 */
 100
 101int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in,
 102                        u16 block_size, u8 bch_level,
 103                        dma_addr_t block_out, dma_addr_t resp);
 104
 105/**
 106 * Ring the BCH doorbell telling it that new commands are
 107 * available.
 108 *
 109 * @param num_commands  Number of new commands
 110 * @param vf            virtual function handle
 111 */
 112static inline void octeontx_bch_write_doorbell(u64 num_commands,
 113                                               struct bch_vf *vf)
 114{
 115        u64 num_words = num_commands * sizeof(union bch_cmd) / sizeof(uint64_t);
 116
 117        writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0));
 118}
 119
 120/**
 121 * Since it's possible (and even likely) that the NAND device will be probed
 122 * before the BCH device has been probed, we may need to defer the probing.
 123 *
 124 * In this case, the initial probe returns success but the actual probing
 125 * is deferred until the BCH VF has been probed.
 126 *
 127 * Return:      0 for success, otherwise error
 128 */
 129int octeontx_pci_nand_deferred_probe(void);
 130
 131#endif /* __OCTEONTX_BCH_H__ */
 132