1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2010 4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 5 */ 6 7#ifndef _DW_ETH_H 8#define _DW_ETH_H 9 10#include <asm/cache.h> 11#include <net.h> 12 13#if CONFIG_IS_ENABLED(DM_GPIO) 14#include <asm-generic/gpio.h> 15#endif 16 17#define CONFIG_TX_DESCR_NUM 16 18#define CONFIG_RX_DESCR_NUM 16 19#define CONFIG_ETH_BUFSIZE 2048 20#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) 21#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) 22 23#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) 24#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) 25 26struct eth_mac_regs { 27 u32 conf; /* 0x00 */ 28 u32 framefilt; /* 0x04 */ 29 u32 hashtablehigh; /* 0x08 */ 30 u32 hashtablelow; /* 0x0c */ 31 u32 miiaddr; /* 0x10 */ 32 u32 miidata; /* 0x14 */ 33 u32 flowcontrol; /* 0x18 */ 34 u32 vlantag; /* 0x1c */ 35 u32 version; /* 0x20 */ 36 u8 reserved_1[20]; 37 u32 intreg; /* 0x38 */ 38 u32 intmask; /* 0x3c */ 39 u32 macaddr0hi; /* 0x40 */ 40 u32 macaddr0lo; /* 0x44 */ 41}; 42 43/* MAC configuration register definitions */ 44#define FRAMEBURSTENABLE (1 << 21) 45#define MII_PORTSELECT (1 << 15) 46#define FES_100 (1 << 14) 47#define DISABLERXOWN (1 << 13) 48#define FULLDPLXMODE (1 << 11) 49#define RXENABLE (1 << 2) 50#define TXENABLE (1 << 3) 51 52/* MII address register definitions */ 53#define MII_BUSY (1 << 0) 54#define MII_WRITE (1 << 1) 55#define MII_CLKRANGE_60_100M (0) 56#define MII_CLKRANGE_100_150M (0x4) 57#define MII_CLKRANGE_20_35M (0x8) 58#define MII_CLKRANGE_35_60M (0xC) 59#define MII_CLKRANGE_150_250M (0x10) 60#define MII_CLKRANGE_250_300M (0x14) 61 62#define MIIADDRSHIFT (11) 63#define MIIREGSHIFT (6) 64#define MII_REGMSK (0x1F << 6) 65#define MII_ADDRMSK (0x1F << 11) 66 67 68struct eth_dma_regs { 69 u32 busmode; /* 0x00 */ 70 u32 txpolldemand; /* 0x04 */ 71 u32 rxpolldemand; /* 0x08 */ 72 u32 rxdesclistaddr; /* 0x0c */ 73 u32 txdesclistaddr; /* 0x10 */ 74 u32 status; /* 0x14 */ 75 u32 opmode; /* 0x18 */ 76 u32 intenable; /* 0x1c */ 77 u32 reserved1[2]; 78 u32 axibus; /* 0x28 */ 79 u32 reserved2[7]; 80 u32 currhosttxdesc; /* 0x48 */ 81 u32 currhostrxdesc; /* 0x4c */ 82 u32 currhosttxbuffaddr; /* 0x50 */ 83 u32 currhostrxbuffaddr; /* 0x54 */ 84}; 85 86#define DW_DMA_BASE_OFFSET (0x1000) 87 88/* Default DMA Burst length */ 89#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL 90#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 91#endif 92 93/* Bus mode register definitions */ 94#define FIXEDBURST (1 << 16) 95#define PRIORXTX_41 (3 << 14) 96#define PRIORXTX_31 (2 << 14) 97#define PRIORXTX_21 (1 << 14) 98#define PRIORXTX_11 (0 << 14) 99#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) 100#define RXHIGHPRIO (1 << 1) 101#define DMAMAC_SRST (1 << 0) 102 103/* Poll demand definitions */ 104#define POLL_DATA (0xFFFFFFFF) 105 106/* Operation mode definitions */ 107#define STOREFORWARD (1 << 21) 108#define FLUSHTXFIFO (1 << 20) 109#define TXSTART (1 << 13) 110#define TXSECONDFRAME (1 << 2) 111#define RXSTART (1 << 1) 112 113/* Descriptior related definitions */ 114#define MAC_MAX_FRAME_SZ (1600) 115 116struct dmamacdescr { 117 u32 txrx_status; 118 u32 dmamac_cntl; 119 u32 dmamac_addr; 120 u32 dmamac_next; 121} __aligned(ARCH_DMA_MINALIGN); 122 123/* 124 * txrx_status definitions 125 */ 126 127/* tx status bits definitions */ 128#if defined(CONFIG_DW_ALTDESCRIPTOR) 129 130#define DESC_TXSTS_OWNBYDMA (1 << 31) 131#define DESC_TXSTS_TXINT (1 << 30) 132#define DESC_TXSTS_TXLAST (1 << 29) 133#define DESC_TXSTS_TXFIRST (1 << 28) 134#define DESC_TXSTS_TXCRCDIS (1 << 27) 135 136#define DESC_TXSTS_TXPADDIS (1 << 26) 137#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) 138#define DESC_TXSTS_TXRINGEND (1 << 21) 139#define DESC_TXSTS_TXCHAIN (1 << 20) 140#define DESC_TXSTS_MSK (0x1FFFF << 0) 141 142#else 143 144#define DESC_TXSTS_OWNBYDMA (1 << 31) 145#define DESC_TXSTS_MSK (0x1FFFF << 0) 146 147#endif 148 149/* rx status bits definitions */ 150#define DESC_RXSTS_OWNBYDMA (1 << 31) 151#define DESC_RXSTS_DAFILTERFAIL (1 << 30) 152#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) 153#define DESC_RXSTS_FRMLENSHFT (16) 154 155#define DESC_RXSTS_ERROR (1 << 15) 156#define DESC_RXSTS_RXTRUNCATED (1 << 14) 157#define DESC_RXSTS_SAFILTERFAIL (1 << 13) 158#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) 159#define DESC_RXSTS_RXDAMAGED (1 << 11) 160#define DESC_RXSTS_RXVLANTAG (1 << 10) 161#define DESC_RXSTS_RXFIRST (1 << 9) 162#define DESC_RXSTS_RXLAST (1 << 8) 163#define DESC_RXSTS_RXIPC_GIANT (1 << 7) 164#define DESC_RXSTS_RXCOLLISION (1 << 6) 165#define DESC_RXSTS_RXFRAMEETHER (1 << 5) 166#define DESC_RXSTS_RXWATCHDOG (1 << 4) 167#define DESC_RXSTS_RXMIIERROR (1 << 3) 168#define DESC_RXSTS_RXDRIBBLING (1 << 2) 169#define DESC_RXSTS_RXCRC (1 << 1) 170 171/* 172 * dmamac_cntl definitions 173 */ 174 175/* tx control bits definitions */ 176#if defined(CONFIG_DW_ALTDESCRIPTOR) 177 178#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) 179#define DESC_TXCTRL_SIZE1SHFT (0) 180#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) 181#define DESC_TXCTRL_SIZE2SHFT (16) 182 183#else 184 185#define DESC_TXCTRL_TXINT (1 << 31) 186#define DESC_TXCTRL_TXLAST (1 << 30) 187#define DESC_TXCTRL_TXFIRST (1 << 29) 188#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) 189#define DESC_TXCTRL_TXCRCDIS (1 << 26) 190#define DESC_TXCTRL_TXRINGEND (1 << 25) 191#define DESC_TXCTRL_TXCHAIN (1 << 24) 192 193#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) 194#define DESC_TXCTRL_SIZE1SHFT (0) 195#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) 196#define DESC_TXCTRL_SIZE2SHFT (11) 197 198#endif 199 200/* rx control bits definitions */ 201#if defined(CONFIG_DW_ALTDESCRIPTOR) 202 203#define DESC_RXCTRL_RXINTDIS (1 << 31) 204#define DESC_RXCTRL_RXRINGEND (1 << 15) 205#define DESC_RXCTRL_RXCHAIN (1 << 14) 206 207#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) 208#define DESC_RXCTRL_SIZE1SHFT (0) 209#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) 210#define DESC_RXCTRL_SIZE2SHFT (16) 211 212#else 213 214#define DESC_RXCTRL_RXINTDIS (1 << 31) 215#define DESC_RXCTRL_RXRINGEND (1 << 25) 216#define DESC_RXCTRL_RXCHAIN (1 << 24) 217 218#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) 219#define DESC_RXCTRL_SIZE1SHFT (0) 220#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) 221#define DESC_RXCTRL_SIZE2SHFT (11) 222 223#endif 224 225struct dw_eth_dev { 226 struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; 227 struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; 228 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 229 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 230 231 u32 interface; 232 u32 max_speed; 233 u32 tx_currdescnum; 234 u32 rx_currdescnum; 235 236 struct eth_mac_regs *mac_regs_p; 237 struct eth_dma_regs *dma_regs_p; 238#ifndef CONFIG_DM_ETH 239 struct eth_device *dev; 240#endif 241#if CONFIG_IS_ENABLED(DM_GPIO) 242 struct gpio_desc reset_gpio; 243#endif 244#ifdef CONFIG_CLK 245 struct clk *clocks; /* clock list */ 246 int clock_count; /* number of clock in clock list */ 247#endif 248 249 struct phy_device *phydev; 250 struct mii_dev *bus; 251}; 252 253#ifdef CONFIG_DM_ETH 254int designware_eth_of_to_plat(struct udevice *dev); 255int designware_eth_probe(struct udevice *dev); 256extern const struct eth_ops designware_eth_ops; 257 258struct dw_eth_pdata { 259 struct eth_pdata eth_pdata; 260 u32 reset_delays[3]; 261}; 262 263int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); 264int designware_eth_enable(struct dw_eth_dev *priv); 265int designware_eth_send(struct udevice *dev, void *packet, int length); 266int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp); 267int designware_eth_free_pkt(struct udevice *dev, uchar *packet, 268 int length); 269void designware_eth_stop(struct udevice *dev); 270int designware_eth_write_hwaddr(struct udevice *dev); 271#endif 272 273#endif 274