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18#ifndef _E1000_HW_H_
19#define _E1000_HW_H_
20
21#include <linux/list.h>
22#include <malloc.h>
23#include <net.h>
24
25#ifndef CONFIG_DM_ETH
26#include <netdev.h>
27#endif
28#include <asm/io.h>
29#include <pci.h>
30
31#ifdef CONFIG_E1000_SPI
32#include <spi.h>
33#endif
34
35#define E1000_ERR(NIC, fmt, args...) \
36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
37
38#ifdef E1000_DEBUG
39#define E1000_DBG(NIC, fmt, args...) \
40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
41#define DEBUGOUT(fmt, args...) printf(fmt ,##args)
42#define DEBUGFUNC() printf("%s\n", __func__);
43#else
44#define E1000_DBG(HW, args...) do { } while (0)
45#define DEBUGFUNC() do { } while (0)
46#define DEBUGOUT(fmt, args...) do { } while (0)
47#endif
48
49
50#define E1000_WRITE_REG(a, reg, value) \
51 writel((value), ((a)->hw_addr + E1000_##reg))
52#define E1000_READ_REG(a, reg) \
53 readl((a)->hw_addr + E1000_##reg)
54#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
56#define E1000_READ_REG_ARRAY(a, reg, offset) \
57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
58#define E1000_WRITE_FLUSH(a) \
59 do { E1000_READ_REG(a, STATUS); } while (0)
60
61
62struct e1000_hw;
63struct e1000_hw_stats;
64
65
66struct e1000_hw *e1000_find_card(unsigned int cardnum);
67
68#ifndef CONFIG_E1000_NO_NVM
69int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
70void e1000_standby_eeprom(struct e1000_hw *hw);
71void e1000_release_eeprom(struct e1000_hw *hw);
72void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
73void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
74#endif
75
76#ifdef CONFIG_E1000_SPI
77int do_e1000_spi(struct cmd_tbl *cmdtp, struct e1000_hw *hw,
78 int argc, char *const argv[]);
79#endif
80
81
82
83typedef enum {
84 e1000_undefined = 0,
85 e1000_82542_rev2_0,
86 e1000_82542_rev2_1,
87 e1000_82543,
88 e1000_82544,
89 e1000_82540,
90 e1000_82545,
91 e1000_82545_rev_3,
92 e1000_82546,
93 e1000_82546_rev_3,
94 e1000_82541,
95 e1000_82541_rev_2,
96 e1000_82547,
97 e1000_82547_rev_2,
98 e1000_82571,
99 e1000_82572,
100 e1000_82573,
101 e1000_82574,
102 e1000_80003es2lan,
103 e1000_ich8lan,
104 e1000_igb,
105 e1000_num_macs
106} e1000_mac_type;
107
108
109typedef enum {
110 e1000_media_type_copper = 0,
111 e1000_media_type_fiber = 1,
112 e1000_media_type_internal_serdes = 2,
113 e1000_num_media_types
114} e1000_media_type;
115
116typedef enum {
117 e1000_eeprom_uninitialized = 0,
118 e1000_eeprom_spi,
119 e1000_eeprom_microwire,
120 e1000_eeprom_flash,
121 e1000_eeprom_ich8,
122 e1000_eeprom_none,
123 e1000_eeprom_invm,
124 e1000_num_eeprom_types
125} e1000_eeprom_type;
126
127typedef enum {
128 e1000_10_half = 0,
129 e1000_10_full = 1,
130 e1000_100_half = 2,
131 e1000_100_full = 3
132} e1000_speed_duplex_type;
133
134
135typedef enum {
136 e1000_fc_none = 0,
137 e1000_fc_rx_pause = 1,
138 e1000_fc_tx_pause = 2,
139 e1000_fc_full = 3,
140 e1000_fc_default = 0xFF
141} e1000_fc_type;
142
143
144typedef enum {
145 e1000_bus_type_unknown = 0,
146 e1000_bus_type_pci,
147 e1000_bus_type_pcix,
148 e1000_bus_type_pci_express,
149 e1000_bus_type_reserved
150} e1000_bus_type;
151
152
153typedef enum {
154 e1000_bus_speed_unknown = 0,
155 e1000_bus_speed_33,
156 e1000_bus_speed_66,
157 e1000_bus_speed_100,
158 e1000_bus_speed_133,
159 e1000_bus_speed_reserved
160} e1000_bus_speed;
161
162
163typedef enum {
164 e1000_bus_width_unknown = 0,
165 e1000_bus_width_32,
166 e1000_bus_width_64
167} e1000_bus_width;
168
169
170typedef enum {
171 e1000_cable_length_50 = 0,
172 e1000_cable_length_50_80,
173 e1000_cable_length_80_110,
174 e1000_cable_length_110_140,
175 e1000_cable_length_140,
176 e1000_cable_length_undefined = 0xFF
177} e1000_cable_length;
178
179typedef enum {
180 e1000_10bt_ext_dist_enable_normal = 0,
181 e1000_10bt_ext_dist_enable_lower,
182 e1000_10bt_ext_dist_enable_undefined = 0xFF
183} e1000_10bt_ext_dist_enable;
184
185typedef enum {
186 e1000_rev_polarity_normal = 0,
187 e1000_rev_polarity_reversed,
188 e1000_rev_polarity_undefined = 0xFF
189} e1000_rev_polarity;
190
191typedef enum {
192 e1000_polarity_reversal_enabled = 0,
193 e1000_polarity_reversal_disabled,
194 e1000_polarity_reversal_undefined = 0xFF
195} e1000_polarity_reversal;
196
197typedef enum {
198 e1000_auto_x_mode_manual_mdi = 0,
199 e1000_auto_x_mode_manual_mdix,
200 e1000_auto_x_mode_auto1,
201 e1000_auto_x_mode_auto2,
202 e1000_auto_x_mode_undefined = 0xFF
203} e1000_auto_x_mode;
204
205typedef enum {
206 e1000_1000t_rx_status_not_ok = 0,
207 e1000_1000t_rx_status_ok,
208 e1000_1000t_rx_status_undefined = 0xFF
209} e1000_1000t_rx_status;
210
211typedef enum {
212 e1000_phy_m88 = 0,
213 e1000_phy_igp,
214 e1000_phy_igp_2,
215 e1000_phy_gg82563,
216 e1000_phy_igp_3,
217 e1000_phy_ife,
218 e1000_phy_igb,
219 e1000_phy_bm,
220 e1000_phy_undefined = 0xFF
221} e1000_phy_type;
222
223struct e1000_phy_info {
224 e1000_cable_length cable_length;
225 e1000_10bt_ext_dist_enable extended_10bt_distance;
226 e1000_rev_polarity cable_polarity;
227 e1000_polarity_reversal polarity_correction;
228 e1000_auto_x_mode mdix_mode;
229 e1000_1000t_rx_status local_rx;
230 e1000_1000t_rx_status remote_rx;
231};
232
233struct e1000_phy_stats {
234 uint32_t idle_errors;
235 uint32_t receive_errors;
236};
237
238
239#define E1000_SUCCESS 0
240#define E1000_ERR_EEPROM 1
241#define E1000_ERR_PHY 2
242#define E1000_ERR_CONFIG 3
243#define E1000_ERR_PARAM 4
244#define E1000_ERR_MAC_TYPE 5
245#define E1000_ERR_PHY_TYPE 6
246#define E1000_ERR_NOLINK 7
247#define E1000_ERR_TIMEOUT 8
248#define E1000_ERR_RESET 9
249#define E1000_ERR_MASTER_REQUESTS_PENDING 10
250#define E1000_ERR_HOST_INTERFACE_COMMAND 11
251#define E1000_BLK_PHY_RESET 12
252#define E1000_ERR_SWFW_SYNC 13
253
254
255#define E1000_DEV_ID_82542 0x1000
256#define E1000_DEV_ID_82543GC_FIBER 0x1001
257#define E1000_DEV_ID_82543GC_COPPER 0x1004
258#define E1000_DEV_ID_82544EI_COPPER 0x1008
259#define E1000_DEV_ID_82544EI_FIBER 0x1009
260#define E1000_DEV_ID_82544GC_COPPER 0x100C
261#define E1000_DEV_ID_82544GC_LOM 0x100D
262#define E1000_DEV_ID_82540EM 0x100E
263#define E1000_DEV_ID_82540EM_LOM 0x1015
264#define E1000_DEV_ID_82540EP_LOM 0x1016
265#define E1000_DEV_ID_82540EP 0x1017
266#define E1000_DEV_ID_82540EP_LP 0x101E
267#define E1000_DEV_ID_82545EM_COPPER 0x100F
268#define E1000_DEV_ID_82545EM_FIBER 0x1011
269#define E1000_DEV_ID_82545GM_COPPER 0x1026
270#define E1000_DEV_ID_82545GM_FIBER 0x1027
271#define E1000_DEV_ID_82545GM_SERDES 0x1028
272#define E1000_DEV_ID_82546EB_COPPER 0x1010
273#define E1000_DEV_ID_82546EB_FIBER 0x1012
274#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
275#define E1000_DEV_ID_82541EI 0x1013
276#define E1000_DEV_ID_82541EI_MOBILE 0x1018
277#define E1000_DEV_ID_82541ER_LOM 0x1014
278#define E1000_DEV_ID_82541ER 0x1078
279#define E1000_DEV_ID_82547GI 0x1075
280#define E1000_DEV_ID_82541GI 0x1076
281#define E1000_DEV_ID_82541GI_MOBILE 0x1077
282#define E1000_DEV_ID_82541GI_LF 0x107C
283#define E1000_DEV_ID_82546GB_COPPER 0x1079
284#define E1000_DEV_ID_82546GB_FIBER 0x107A
285#define E1000_DEV_ID_82546GB_SERDES 0x107B
286#define E1000_DEV_ID_82546GB_PCIE 0x108A
287#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
288#define E1000_DEV_ID_82547EI 0x1019
289#define E1000_DEV_ID_82547EI_MOBILE 0x101A
290#define E1000_DEV_ID_82571EB_COPPER 0x105E
291#define E1000_DEV_ID_82571EB_FIBER 0x105F
292#define E1000_DEV_ID_82571EB_SERDES 0x1060
293#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
294#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
295#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
296#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
297#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
298#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
299#define E1000_DEV_ID_82572EI_COPPER 0x107D
300#define E1000_DEV_ID_82572EI_FIBER 0x107E
301#define E1000_DEV_ID_82572EI_SERDES 0x107F
302#define E1000_DEV_ID_82572EI 0x10B9
303#define E1000_DEV_ID_82573E 0x108B
304#define E1000_DEV_ID_82573E_IAMT 0x108C
305#define E1000_DEV_ID_82573L 0x109A
306#define E1000_DEV_ID_82574L 0x10D3
307#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
308#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
309#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
310#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
311#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
312
313#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
314#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
315#define E1000_DEV_ID_ICH8_IGP_C 0x104B
316#define E1000_DEV_ID_ICH8_IFE 0x104C
317#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
318#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
319#define E1000_DEV_ID_ICH8_IGP_M 0x104D
320
321#define IGP03E1000_E_PHY_ID 0x02A80390
322#define IFE_E_PHY_ID 0x02A80330
323#define IFE_PLUS_E_PHY_ID 0x02A80320
324#define IFE_C_E_PHY_ID 0x02A80310
325
326#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
327
328#define IFE_PHY_SPECIAL_CONTROL 0x11
329
330#define IFE_PHY_RCV_FALSE_CARRIER 0x13
331
332#define IFE_PHY_RCV_DISCONNECT 0x14
333
334#define IFE_PHY_RCV_ERROT_FRAME 0x15
335
336#define IFE_PHY_RCV_SYMBOL_ERR 0x16
337
338#define IFE_PHY_PREM_EOF_ERR 0x17
339
340
341#define IFE_PHY_RCV_EOF_ERR 0x18
342
343#define IFE_PHY_TX_JABBER_DETECT 0x19
344
345#define IFE_PHY_EQUALIZER 0x1A
346
347#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B
348
349#define IFE_PHY_MDIX_CONTROL 0x1C
350#define IFE_PHY_HWI_CONTROL 0x1D
351
352
353#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000
354
355#define IFE_PESC_100BTX_POWER_DOWN 0x0400
356
357#define IFE_PESC_10BTX_POWER_DOWN 0x0200
358
359#define IFE_PESC_POLARITY_REVERSED 0x0100
360
361#define IFE_PESC_PHY_ADDR_MASK 0x007C
362
363#define IFE_PESC_SPEED 0x0002
364
365#define IFE_PESC_DUPLEX 0x0001
366
367#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
368
369#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
370
371#define IFE_PSC_FORCE_POLARITY 0x0020
372
373#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
374
375#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001
376
377#define IFE_PSC_FORCE_POLARITY_SHIFT 5
378#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
379
380#define IFE_PMC_AUTO_MDIX 0x0080
381
382#define IFE_PMC_FORCE_MDIX 0x0040
383
384#define IFE_PMC_MDIX_STATUS 0x0020
385#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010
386
387#define IFE_PMC_MDIX_MODE_SHIFT 6
388#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000
389
390#define IFE_PHC_HWI_ENABLE 0x8000
391
392#define IFE_PHC_ABILITY_CHECK 0x4000
393
394#define IFE_PHC_TEST_EXEC 0x2000
395
396#define IFE_PHC_HIGHZ 0x0200
397#define IFE_PHC_LOWZ 0x0400
398#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600
399
400#define IFE_PHC_DISTANCE_MASK 0x01FF
401
402#define IFE_PHC_RESET_ALL_MASK 0x0000
403#define IFE_PSCL_PROBE_MODE 0x0020
404#define IFE_PSCL_PROBE_LEDS_OFF 0x0006
405
406#define IFE_PSCL_PROBE_LEDS_ON 0x0007
407
408
409#define NUM_DEV_IDS 16
410
411#define NODE_ADDRESS_SIZE 6
412#define ETH_LENGTH_OF_ADDRESS 6
413
414
415#define MAC_DECODE_SIZE (128 * 1024)
416
417#define E1000_82542_2_0_REV_ID 2
418#define E1000_82542_2_1_REV_ID 3
419#define E1000_REVISION_0 0
420#define E1000_REVISION_1 1
421#define E1000_REVISION_2 2
422#define E1000_REVISION_3 3
423
424#define SPEED_10 10
425#define SPEED_100 100
426#define SPEED_1000 1000
427#define HALF_DUPLEX 1
428#define FULL_DUPLEX 2
429
430
431#define ENET_HEADER_SIZE 14
432#define MAXIMUM_ETHERNET_FRAME_SIZE 1518
433#define MINIMUM_ETHERNET_FRAME_SIZE 64
434#define MAXIMUM_ETHERNET_PACKET_SIZE \
435 (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
436#define MINIMUM_ETHERNET_PACKET_SIZE \
437 (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
438#define CRC_LENGTH ETH_FCS_LEN
439#define MAX_JUMBO_FRAME_SIZE 0x3F00
440
441
442#define VLAN_TAG_SIZE 4
443
444
445#define ETHERNET_IEEE_VLAN_TYPE 0x8100
446#define ETHERNET_IP_TYPE 0x0800
447#define ETHERNET_ARP_TYPE 0x0806
448
449
450#define IP_PROTOCOL_TCP 6
451#define IP_PROTOCOL_UDP 0x11
452
453
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456
457
458#define POLL_IMS_ENABLE_MASK ( \
459 E1000_IMS_RXDMT0 | \
460 E1000_IMS_RXSEQ)
461
462
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468
469
470#define IMS_ENABLE_MASK ( \
471 E1000_IMS_RXT0 | \
472 E1000_IMS_TXDW | \
473 E1000_IMS_RXDMT0 | \
474 E1000_IMS_RXSEQ | \
475 E1000_IMS_LSC)
476
477
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479
480
481
482#define E1000_RAR_ENTRIES 16
483
484#define MIN_NUMBER_OF_DESCRIPTORS 8
485#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
486
487
488struct e1000_rx_desc {
489 uint64_t buffer_addr;
490 uint16_t length;
491 uint16_t csum;
492 uint8_t status;
493 uint8_t errors;
494 uint16_t special;
495};
496
497
498#define E1000_RXD_STAT_DD 0x01
499#define E1000_RXD_STAT_EOP 0x02
500#define E1000_RXD_STAT_IXSM 0x04
501#define E1000_RXD_STAT_VP 0x08
502#define E1000_RXD_STAT_TCPCS 0x20
503#define E1000_RXD_STAT_IPCS 0x40
504#define E1000_RXD_STAT_PIF 0x80
505#define E1000_RXD_ERR_CE 0x01
506#define E1000_RXD_ERR_SE 0x02
507#define E1000_RXD_ERR_SEQ 0x04
508#define E1000_RXD_ERR_CXE 0x10
509#define E1000_RXD_ERR_TCPE 0x20
510#define E1000_RXD_ERR_IPE 0x40
511#define E1000_RXD_ERR_RXE 0x80
512#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
513#define E1000_RXD_SPC_PRI_MASK 0xE000
514#define E1000_RXD_SPC_PRI_SHIFT 0x000D
515#define E1000_RXD_SPC_CFI_MASK 0x1000
516#define E1000_RXD_SPC_CFI_SHIFT 0x000C
517
518
519#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
520 E1000_RXD_ERR_CE | \
521 E1000_RXD_ERR_SE | \
522 E1000_RXD_ERR_SEQ | \
523 E1000_RXD_ERR_CXE | \
524 E1000_RXD_ERR_RXE)
525
526
527struct e1000_tx_desc {
528 uint64_t buffer_addr;
529 union {
530 uint32_t data;
531 struct {
532 uint16_t length;
533 uint8_t cso;
534 uint8_t cmd;
535 } flags;
536 } lower;
537 union {
538 uint32_t data;
539 struct {
540 uint8_t status;
541 uint8_t css;
542 uint16_t special;
543 } fields;
544 } upper;
545};
546
547
548#define E1000_TXD_DTYP_D 0x00100000
549#define E1000_TXD_DTYP_C 0x00000000
550#define E1000_TXD_POPTS_IXSM 0x01
551#define E1000_TXD_POPTS_TXSM 0x02
552#define E1000_TXD_CMD_EOP 0x01000000
553#define E1000_TXD_CMD_IFCS 0x02000000
554#define E1000_TXD_CMD_IC 0x04000000
555#define E1000_TXD_CMD_RS 0x08000000
556#define E1000_TXD_CMD_RPS 0x10000000
557#define E1000_TXD_CMD_DEXT 0x20000000
558#define E1000_TXD_CMD_VLE 0x40000000
559#define E1000_TXD_CMD_IDE 0x80000000
560#define E1000_TXD_STAT_DD 0x00000001
561#define E1000_TXD_STAT_EC 0x00000002
562#define E1000_TXD_STAT_LC 0x00000004
563#define E1000_TXD_STAT_TU 0x00000008
564#define E1000_TXD_CMD_TCP 0x01000000
565#define E1000_TXD_CMD_IP 0x02000000
566#define E1000_TXD_CMD_TSE 0x04000000
567#define E1000_TXD_STAT_TC 0x00000004
568
569
570struct e1000_context_desc {
571 union {
572 uint32_t ip_config;
573 struct {
574 uint8_t ipcss;
575 uint8_t ipcso;
576 uint16_t ipcse;
577 } ip_fields;
578 } lower_setup;
579 union {
580 uint32_t tcp_config;
581 struct {
582 uint8_t tucss;
583 uint8_t tucso;
584 uint16_t tucse;
585 } tcp_fields;
586 } upper_setup;
587 uint32_t cmd_and_length;
588 union {
589 uint32_t data;
590 struct {
591 uint8_t status;
592 uint8_t hdr_len;
593 uint16_t mss;
594 } fields;
595 } tcp_seg_setup;
596};
597
598
599struct e1000_data_desc {
600 uint64_t buffer_addr;
601 union {
602 uint32_t data;
603 struct {
604 uint16_t length;
605 uint8_t typ_len_ext;
606 uint8_t cmd;
607 } flags;
608 } lower;
609 union {
610 uint32_t data;
611 struct {
612 uint8_t status;
613 uint8_t popts;
614 uint16_t special;
615 } fields;
616 } upper;
617};
618
619
620#define E1000_NUM_UNICAST 16
621#define E1000_MC_TBL_SIZE 128
622#define E1000_VLAN_FILTER_TBL_SIZE 128
623
624
625struct e1000_rar {
626 volatile uint32_t low;
627 volatile uint32_t high;
628};
629
630
631#define E1000_NUM_MTA_REGISTERS 128
632
633
634struct e1000_ipv4_at_entry {
635 volatile uint32_t ipv4_addr;
636 volatile uint32_t reserved;
637};
638
639
640#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
641#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
642#define E1000_IP6AT_SIZE 1
643
644
645struct e1000_ipv6_at_entry {
646 volatile uint8_t ipv6_addr[16];
647};
648
649
650struct e1000_fflt_entry {
651 volatile uint32_t length;
652 volatile uint32_t reserved;
653};
654
655
656struct e1000_ffmt_entry {
657 volatile uint32_t mask;
658 volatile uint32_t reserved;
659};
660
661
662struct e1000_ffvt_entry {
663 volatile uint32_t value;
664 volatile uint32_t reserved;
665};
666
667
668#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
669
670
671#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
672
673#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
674#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
675#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
676
677
678
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685
686
687
688
689#define E1000_CTRL 0x00000
690#define E1000_STATUS 0x00008
691#define E1000_EECD 0x00010
692#define E1000_I210_EECD 0x12010
693#define E1000_EERD 0x00014
694#define E1000_I210_EERD 0x12014
695#define E1000_CTRL_EXT 0x00018
696#define E1000_MDIC 0x00020
697#define E1000_FCAL 0x00028
698#define E1000_FCAH 0x0002C
699#define E1000_FCT 0x00030
700#define E1000_VET 0x00038
701#define E1000_ICR 0x000C0
702#define E1000_ITR 0x000C4
703#define E1000_ICS 0x000C8
704#define E1000_IMS 0x000D0
705#define E1000_IMC 0x000D8
706#define E1000_I210_IAM 0x000E0
707#define E1000_RCTL 0x00100
708#define E1000_FCTTV 0x00170
709#define E1000_TXCW 0x00178
710#define E1000_RXCW 0x00180
711#define E1000_TCTL 0x00400
712#define E1000_TCTL_EXT 0x00404
713#define E1000_TIPG 0x00410
714#define E1000_TBT 0x00448
715#define E1000_AIT 0x00458
716#define E1000_LEDCTL 0x00E00
717#define E1000_EXTCNF_CTRL 0x00F00
718#define E1000_EXTCNF_SIZE 0x00F08
719#define E1000_PHY_CTRL 0x00F10
720#define E1000_I210_PHY_CTRL 0x00E14
721#define FEXTNVM_SW_CONFIG 0x0001
722#define E1000_PBA 0x01000
723#define E1000_PBS 0x01008
724#define E1000_EEMNGCTL 0x01010
725#define E1000_I210_EEMNGCTL 0x12030
726#define E1000_FLASH_UPDATES 1000
727#define E1000_EEARBC 0x01024
728#define E1000_FLASHT 0x01028
729#define E1000_EEWR 0x0102C
730#define E1000_I210_EEWR 0x12018
731#define E1000_FLSWCTL 0x01030
732#define E1000_FLSWDATA 0x01034
733#define E1000_FLSWCNT 0x01038
734#define E1000_FLOP 0x0103C
735#define E1000_ERT 0x02008
736#define E1000_FCRTL 0x02160
737#define E1000_FCRTH 0x02168
738#define E1000_RXPBS 0x02404
739#define E1000_RDBAL 0x02800
740#define E1000_RDBAH 0x02804
741#define E1000_RDLEN 0x02808
742#define E1000_RDH 0x02810
743#define E1000_RDT 0x02818
744#define E1000_RDTR 0x02820
745#define E1000_RXDCTL 0x02828
746#define E1000_RADV 0x0282C
747#define E1000_RSRPD 0x02C00
748#define E1000_TXDMAC 0x03000
749#define E1000_TXPBS 0x03404
750#define E1000_TDFH 0x03410
751#define E1000_TDFT 0x03418
752#define E1000_TDFHS 0x03420
753#define E1000_TDFTS 0x03428
754#define E1000_TDFPC 0x03430
755#define E1000_TDBAL 0x03800
756#define E1000_TDBAH 0x03804
757#define E1000_TDLEN 0x03808
758#define E1000_TDH 0x03810
759#define E1000_TDT 0x03818
760#define E1000_TIDV 0x03820
761#define E1000_TXDCTL 0x03828
762#define E1000_TADV 0x0382C
763#define E1000_TSPMT 0x03830
764#define E1000_TARC0 0x03840
765#define E1000_TDBAL1 0x03900
766#define E1000_TDBAH1 0x03904
767#define E1000_TDLEN1 0x03908
768#define E1000_TDH1 0x03910
769#define E1000_TDT1 0x03918
770#define E1000_TXDCTL1 0x03928
771#define E1000_TARC1 0x03940
772#define E1000_CRCERRS 0x04000
773#define E1000_ALGNERRC 0x04004
774#define E1000_SYMERRS 0x04008
775#define E1000_RXERRC 0x0400C
776#define E1000_MPC 0x04010
777#define E1000_SCC 0x04014
778#define E1000_ECOL 0x04018
779#define E1000_MCC 0x0401C
780#define E1000_LATECOL 0x04020
781#define E1000_COLC 0x04028
782#define E1000_DC 0x04030
783#define E1000_TNCRS 0x04034
784#define E1000_SEC 0x04038
785#define E1000_CEXTERR 0x0403C
786#define E1000_RLEC 0x04040
787#define E1000_XONRXC 0x04048
788#define E1000_XONTXC 0x0404C
789#define E1000_XOFFRXC 0x04050
790#define E1000_XOFFTXC 0x04054
791#define E1000_FCRUC 0x04058
792#define E1000_PRC64 0x0405C
793#define E1000_PRC127 0x04060
794#define E1000_PRC255 0x04064
795#define E1000_PRC511 0x04068
796#define E1000_PRC1023 0x0406C
797#define E1000_PRC1522 0x04070
798#define E1000_GPRC 0x04074
799#define E1000_BPRC 0x04078
800#define E1000_MPRC 0x0407C
801#define E1000_GPTC 0x04080
802#define E1000_GORCL 0x04088
803#define E1000_GORCH 0x0408C
804#define E1000_GOTCL 0x04090
805#define E1000_GOTCH 0x04094
806#define E1000_RNBC 0x040A0
807#define E1000_RUC 0x040A4
808#define E1000_RFC 0x040A8
809#define E1000_ROC 0x040AC
810#define E1000_RJC 0x040B0
811#define E1000_MGTPRC 0x040B4
812#define E1000_MGTPDC 0x040B8
813#define E1000_MGTPTC 0x040BC
814#define E1000_TORL 0x040C0
815#define E1000_TORH 0x040C4
816#define E1000_TOTL 0x040C8
817#define E1000_TOTH 0x040CC
818#define E1000_TPR 0x040D0
819#define E1000_TPT 0x040D4
820#define E1000_PTC64 0x040D8
821#define E1000_PTC127 0x040DC
822#define E1000_PTC255 0x040E0
823#define E1000_PTC511 0x040E4
824#define E1000_PTC1023 0x040E8
825#define E1000_PTC1522 0x040EC
826#define E1000_MPTC 0x040F0
827#define E1000_BPTC 0x040F4
828#define E1000_TSCTC 0x040F8
829#define E1000_TSCTFC 0x040FC
830#define E1000_RXCSUM 0x05000
831#define E1000_MTA 0x05200
832#define E1000_RA 0x05400
833#define E1000_VFTA 0x05600
834#define E1000_WUC 0x05800
835#define E1000_WUFC 0x05808
836#define E1000_WUS 0x05810
837#define E1000_MANC 0x05820
838#define E1000_IPAV 0x05838
839#define E1000_IP4AT 0x05840
840#define E1000_IP6AT 0x05880
841#define E1000_WUPL 0x05900
842#define E1000_WUPM 0x05A00
843#define E1000_FFLT 0x05F00
844#define E1000_FFMT 0x09000
845#define E1000_FFVT 0x09800
846
847
848
849
850
851
852
853#define E1000_82542_CTRL E1000_CTRL
854#define E1000_82542_STATUS E1000_STATUS
855#define E1000_82542_EECD E1000_EECD
856#define E1000_82542_EERD E1000_EERD
857#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
858#define E1000_82542_MDIC E1000_MDIC
859#define E1000_82542_FCAL E1000_FCAL
860#define E1000_82542_FCAH E1000_FCAH
861#define E1000_82542_FCT E1000_FCT
862#define E1000_82542_VET E1000_VET
863#define E1000_82542_RA 0x00040
864#define E1000_82542_ICR E1000_ICR
865#define E1000_82542_ITR E1000_ITR
866#define E1000_82542_ICS E1000_ICS
867#define E1000_82542_IMS E1000_IMS
868#define E1000_82542_IMC E1000_IMC
869#define E1000_82542_RCTL E1000_RCTL
870#define E1000_82542_RDTR 0x00108
871#define E1000_82542_RDBAL 0x00110
872#define E1000_82542_RDBAH 0x00114
873#define E1000_82542_RDLEN 0x00118
874#define E1000_82542_RDH 0x00120
875#define E1000_82542_RDT 0x00128
876#define E1000_82542_FCRTH 0x00160
877#define E1000_82542_FCRTL 0x00168
878#define E1000_82542_FCTTV E1000_FCTTV
879#define E1000_82542_TXCW E1000_TXCW
880#define E1000_82542_RXCW E1000_RXCW
881#define E1000_82542_MTA 0x00200
882#define E1000_82542_TCTL E1000_TCTL
883#define E1000_82542_TIPG E1000_TIPG
884#define E1000_82542_TDBAL 0x00420
885#define E1000_82542_TDBAH 0x00424
886#define E1000_82542_TDLEN 0x00428
887#define E1000_82542_TDH 0x00430
888#define E1000_82542_TDT 0x00438
889#define E1000_82542_TIDV 0x00440
890#define E1000_82542_TBT E1000_TBT
891#define E1000_82542_AIT E1000_AIT
892#define E1000_82542_VFTA 0x00600
893#define E1000_82542_LEDCTL E1000_LEDCTL
894#define E1000_82542_PBA E1000_PBA
895#define E1000_82542_RXDCTL E1000_RXDCTL
896#define E1000_82542_RADV E1000_RADV
897#define E1000_82542_RSRPD E1000_RSRPD
898#define E1000_82542_TXDMAC E1000_TXDMAC
899#define E1000_82542_TXDCTL E1000_TXDCTL
900#define E1000_82542_TADV E1000_TADV
901#define E1000_82542_TSPMT E1000_TSPMT
902#define E1000_82542_CRCERRS E1000_CRCERRS
903#define E1000_82542_ALGNERRC E1000_ALGNERRC
904#define E1000_82542_SYMERRS E1000_SYMERRS
905#define E1000_82542_RXERRC E1000_RXERRC
906#define E1000_82542_MPC E1000_MPC
907#define E1000_82542_SCC E1000_SCC
908#define E1000_82542_ECOL E1000_ECOL
909#define E1000_82542_MCC E1000_MCC
910#define E1000_82542_LATECOL E1000_LATECOL
911#define E1000_82542_COLC E1000_COLC
912#define E1000_82542_DC E1000_DC
913#define E1000_82542_TNCRS E1000_TNCRS
914#define E1000_82542_SEC E1000_SEC
915#define E1000_82542_CEXTERR E1000_CEXTERR
916#define E1000_82542_RLEC E1000_RLEC
917#define E1000_82542_XONRXC E1000_XONRXC
918#define E1000_82542_XONTXC E1000_XONTXC
919#define E1000_82542_XOFFRXC E1000_XOFFRXC
920#define E1000_82542_XOFFTXC E1000_XOFFTXC
921#define E1000_82542_FCRUC E1000_FCRUC
922#define E1000_82542_PRC64 E1000_PRC64
923#define E1000_82542_PRC127 E1000_PRC127
924#define E1000_82542_PRC255 E1000_PRC255
925#define E1000_82542_PRC511 E1000_PRC511
926#define E1000_82542_PRC1023 E1000_PRC1023
927#define E1000_82542_PRC1522 E1000_PRC1522
928#define E1000_82542_GPRC E1000_GPRC
929#define E1000_82542_BPRC E1000_BPRC
930#define E1000_82542_MPRC E1000_MPRC
931#define E1000_82542_GPTC E1000_GPTC
932#define E1000_82542_GORCL E1000_GORCL
933#define E1000_82542_GORCH E1000_GORCH
934#define E1000_82542_GOTCL E1000_GOTCL
935#define E1000_82542_GOTCH E1000_GOTCH
936#define E1000_82542_RNBC E1000_RNBC
937#define E1000_82542_RUC E1000_RUC
938#define E1000_82542_RFC E1000_RFC
939#define E1000_82542_ROC E1000_ROC
940#define E1000_82542_RJC E1000_RJC
941#define E1000_82542_MGTPRC E1000_MGTPRC
942#define E1000_82542_MGTPDC E1000_MGTPDC
943#define E1000_82542_MGTPTC E1000_MGTPTC
944#define E1000_82542_TORL E1000_TORL
945#define E1000_82542_TORH E1000_TORH
946#define E1000_82542_TOTL E1000_TOTL
947#define E1000_82542_TOTH E1000_TOTH
948#define E1000_82542_TPR E1000_TPR
949#define E1000_82542_TPT E1000_TPT
950#define E1000_82542_PTC64 E1000_PTC64
951#define E1000_82542_PTC127 E1000_PTC127
952#define E1000_82542_PTC255 E1000_PTC255
953#define E1000_82542_PTC511 E1000_PTC511
954#define E1000_82542_PTC1023 E1000_PTC1023
955#define E1000_82542_PTC1522 E1000_PTC1522
956#define E1000_82542_MPTC E1000_MPTC
957#define E1000_82542_BPTC E1000_BPTC
958#define E1000_82542_TSCTC E1000_TSCTC
959#define E1000_82542_TSCTFC E1000_TSCTFC
960#define E1000_82542_RXCSUM E1000_RXCSUM
961#define E1000_82542_WUC E1000_WUC
962#define E1000_82542_WUFC E1000_WUFC
963#define E1000_82542_WUS E1000_WUS
964#define E1000_82542_MANC E1000_MANC
965#define E1000_82542_IPAV E1000_IPAV
966#define E1000_82542_IP4AT E1000_IP4AT
967#define E1000_82542_IP6AT E1000_IP6AT
968#define E1000_82542_WUPL E1000_WUPL
969#define E1000_82542_WUPM E1000_WUPM
970#define E1000_82542_FFLT E1000_FFLT
971#define E1000_82542_FFMT E1000_FFMT
972#define E1000_82542_FFVT E1000_FFVT
973
974
975struct e1000_hw_stats {
976 uint64_t crcerrs;
977 uint64_t algnerrc;
978 uint64_t symerrs;
979 uint64_t rxerrc;
980 uint64_t mpc;
981 uint64_t scc;
982 uint64_t ecol;
983 uint64_t mcc;
984 uint64_t latecol;
985 uint64_t colc;
986 uint64_t dc;
987 uint64_t tncrs;
988 uint64_t sec;
989 uint64_t cexterr;
990 uint64_t rlec;
991 uint64_t xonrxc;
992 uint64_t xontxc;
993 uint64_t xoffrxc;
994 uint64_t xofftxc;
995 uint64_t fcruc;
996 uint64_t prc64;
997 uint64_t prc127;
998 uint64_t prc255;
999 uint64_t prc511;
1000 uint64_t prc1023;
1001 uint64_t prc1522;
1002 uint64_t gprc;
1003 uint64_t bprc;
1004 uint64_t mprc;
1005 uint64_t gptc;
1006 uint64_t gorcl;
1007 uint64_t gorch;
1008 uint64_t gotcl;
1009 uint64_t gotch;
1010 uint64_t rnbc;
1011 uint64_t ruc;
1012 uint64_t rfc;
1013 uint64_t roc;
1014 uint64_t rjc;
1015 uint64_t mgprc;
1016 uint64_t mgpdc;
1017 uint64_t mgptc;
1018 uint64_t torl;
1019 uint64_t torh;
1020 uint64_t totl;
1021 uint64_t toth;
1022 uint64_t tpr;
1023 uint64_t tpt;
1024 uint64_t ptc64;
1025 uint64_t ptc127;
1026 uint64_t ptc255;
1027 uint64_t ptc511;
1028 uint64_t ptc1023;
1029 uint64_t ptc1522;
1030 uint64_t mptc;
1031 uint64_t bptc;
1032 uint64_t tsctc;
1033 uint64_t tsctfc;
1034};
1035
1036#ifndef CONFIG_E1000_NO_NVM
1037struct e1000_eeprom_info {
1038e1000_eeprom_type type;
1039 uint16_t word_size;
1040 uint16_t opcode_bits;
1041 uint16_t address_bits;
1042 uint16_t delay_usec;
1043 uint16_t page_size;
1044 bool use_eerd;
1045 bool use_eewr;
1046};
1047#endif
1048
1049typedef enum {
1050 e1000_smart_speed_default = 0,
1051 e1000_smart_speed_on,
1052 e1000_smart_speed_off
1053} e1000_smart_speed;
1054
1055typedef enum {
1056 e1000_dsp_config_disabled = 0,
1057 e1000_dsp_config_enabled,
1058 e1000_dsp_config_activated,
1059 e1000_dsp_config_undefined = 0xFF
1060} e1000_dsp_config;
1061
1062typedef enum {
1063 e1000_ms_hw_default = 0,
1064 e1000_ms_force_master,
1065 e1000_ms_force_slave,
1066 e1000_ms_auto
1067} e1000_ms_type;
1068
1069typedef enum {
1070 e1000_ffe_config_enabled = 0,
1071 e1000_ffe_config_active,
1072 e1000_ffe_config_blocked
1073} e1000_ffe_config;
1074
1075
1076
1077struct e1000_hw {
1078 const char *name;
1079 struct list_head list_node;
1080#ifndef CONFIG_DM_ETH
1081 struct eth_device *nic;
1082#endif
1083#ifdef CONFIG_E1000_SPI
1084 struct spi_slave spi;
1085#endif
1086 unsigned int cardnum;
1087
1088#ifdef CONFIG_DM_ETH
1089 struct udevice *pdev;
1090#else
1091 pci_dev_t pdev;
1092#endif
1093 uint8_t *hw_addr;
1094 e1000_mac_type mac_type;
1095 e1000_phy_type phy_type;
1096 uint32_t phy_init_script;
1097 uint32_t txd_cmd;
1098 e1000_media_type media_type;
1099 e1000_fc_type fc;
1100 e1000_bus_type bus_type;
1101 uint32_t asf_firmware_present;
1102#ifndef CONFIG_E1000_NO_NVM
1103 uint32_t eeprom_semaphore_present;
1104#endif
1105 uint32_t swfw_sync_present;
1106 uint32_t swfwhw_semaphore_present;
1107#ifndef CONFIG_E1000_NO_NVM
1108 struct e1000_eeprom_info eeprom;
1109#endif
1110 e1000_ms_type master_slave;
1111 e1000_ms_type original_master_slave;
1112 e1000_ffe_config ffe_config_state;
1113 uint32_t phy_id;
1114 uint32_t phy_revision;
1115 uint32_t phy_addr;
1116 uint32_t original_fc;
1117 uint32_t txcw;
1118 uint32_t autoneg_failed;
1119 uint16_t autoneg_advertised;
1120 uint16_t pci_cmd_word;
1121 uint16_t fc_high_water;
1122 uint16_t fc_low_water;
1123 uint16_t fc_pause_time;
1124 uint16_t device_id;
1125 uint16_t vendor_id;
1126 uint16_t subsystem_id;
1127 uint16_t subsystem_vendor_id;
1128 uint8_t revision_id;
1129 uint8_t autoneg;
1130 uint8_t mdix;
1131 uint8_t forced_speed_duplex;
1132 uint8_t wait_autoneg_complete;
1133 uint8_t dma_fairness;
1134 bool disable_polarity_correction;
1135 bool speed_downgraded;
1136 bool get_link_status;
1137 bool tbi_compatibility_en;
1138 bool tbi_compatibility_on;
1139 bool fc_strict_ieee;
1140 bool fc_send_xon;
1141 bool report_tx_early;
1142 bool phy_reset_disable;
1143 bool initialize_hw_bits_disable;
1144 e1000_smart_speed smart_speed;
1145 e1000_dsp_config dsp_config_state;
1146};
1147
1148#define E1000_EEPROM_SWDPIN0 0x0001
1149#define E1000_EEPROM_LED_LOGIC 0x0020
1150#define E1000_EEPROM_RW_REG_DATA 16
1151
1152#define E1000_EEPROM_RW_REG_DONE 2
1153#define E1000_EEPROM_RW_REG_START 1
1154
1155#define E1000_EEPROM_RW_ADDR_SHIFT 2
1156#define E1000_EEPROM_POLL_WRITE 1
1157
1158#define E1000_EEPROM_POLL_READ 0
1159#define EEPROM_RESERVED_WORD 0xFFFF
1160
1161
1162
1163#define E1000_CTRL_FD 0x00000001
1164#define E1000_CTRL_BEM 0x00000002
1165#define E1000_CTRL_PRIOR 0x00000004
1166#define E1000_CTRL_LRST 0x00000008
1167#define E1000_CTRL_TME 0x00000010
1168#define E1000_CTRL_SLE 0x00000020
1169#define E1000_CTRL_ASDE 0x00000020
1170#define E1000_CTRL_SLU 0x00000040
1171#define E1000_CTRL_ILOS 0x00000080
1172#define E1000_CTRL_SPD_SEL 0x00000300
1173#define E1000_CTRL_SPD_10 0x00000000
1174#define E1000_CTRL_SPD_100 0x00000100
1175#define E1000_CTRL_SPD_1000 0x00000200
1176#define E1000_CTRL_BEM32 0x00000400
1177#define E1000_CTRL_FRCSPD 0x00000800
1178#define E1000_CTRL_FRCDPX 0x00001000
1179#define E1000_CTRL_SWDPIN0 0x00040000
1180#define E1000_CTRL_SWDPIN1 0x00080000
1181#define E1000_CTRL_SWDPIN2 0x00100000
1182#define E1000_CTRL_SWDPIN3 0x00200000
1183#define E1000_CTRL_SWDPIO0 0x00400000
1184#define E1000_CTRL_SWDPIO1 0x00800000
1185#define E1000_CTRL_SWDPIO2 0x01000000
1186#define E1000_CTRL_SWDPIO3 0x02000000
1187#define E1000_CTRL_RST 0x04000000
1188#define E1000_CTRL_RFCE 0x08000000
1189#define E1000_CTRL_TFCE 0x10000000
1190#define E1000_CTRL_RTE 0x20000000
1191#define E1000_CTRL_VME 0x40000000
1192#define E1000_CTRL_PHY_RST 0x80000000
1193
1194
1195#define E1000_STATUS_FD 0x00000001
1196#define E1000_STATUS_LU 0x00000002
1197#define E1000_STATUS_FUNC_MASK 0x0000000C
1198#define E1000_STATUS_FUNC_0 0x00000000
1199#define E1000_STATUS_FUNC_1 0x00000004
1200#define E1000_STATUS_TXOFF 0x00000010
1201#define E1000_STATUS_TBIMODE 0x00000020
1202#define E1000_STATUS_SPEED_MASK 0x000000C0
1203#define E1000_STATUS_SPEED_10 0x00000000
1204#define E1000_STATUS_SPEED_100 0x00000040
1205#define E1000_STATUS_SPEED_1000 0x00000080
1206#define E1000_STATUS_ASDV 0x00000300
1207#define E1000_STATUS_MTXCKOK 0x00000400
1208#define E1000_STATUS_PCI66 0x00000800
1209#define E1000_STATUS_BUS64 0x00001000
1210#define E1000_STATUS_PCIX_MODE 0x00002000
1211#define E1000_STATUS_PCIX_SPEED 0x0000C000
1212#define E1000_STATUS_PF_RST_DONE 0x00200000
1213
1214
1215#define E1000_STATUS_PCIX_SPEED_66 0x00000000
1216#define E1000_STATUS_PCIX_SPEED_100 0x00004000
1217#define E1000_STATUS_PCIX_SPEED_133 0x00008000
1218
1219
1220#define E1000_EECD_SK 0x00000001
1221#define E1000_EECD_CS 0x00000002
1222#define E1000_EECD_DI 0x00000004
1223#define E1000_EECD_DO 0x00000008
1224#define E1000_EECD_FWE_MASK 0x00000030
1225#define E1000_EECD_FWE_DIS 0x00000010
1226#define E1000_EECD_FWE_EN 0x00000020
1227#define E1000_EECD_FWE_SHIFT 4
1228#define E1000_EECD_SIZE 0x00000200
1229#define E1000_EECD_REQ 0x00000040
1230#define E1000_EECD_GNT 0x00000080
1231#define E1000_EECD_PRES 0x00000100
1232#define E1000_EECD_ADDR_BITS 0x00000400
1233
1234
1235#define E1000_EECD_TYPE 0x00002000
1236#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1237#define E1000_EEPROM_GRANT_ATTEMPTS 1000
1238#endif
1239#define E1000_EECD_AUTO_RD 0x00000200
1240#define E1000_EECD_SIZE_EX_MASK 0x00007800
1241#define E1000_EECD_SIZE_EX_SHIFT 11
1242#define E1000_EECD_NVADDS 0x00018000
1243#define E1000_EECD_SELSHAD 0x00020000
1244#define E1000_EECD_INITSRAM 0x00040000
1245#define E1000_EECD_FLUPD 0x00080000
1246#define E1000_EECD_FLUPD_I210 0x00800000
1247#define E1000_EECD_FLUDONE_I210 0x04000000
1248#define E1000_EECD_FLASH_DETECTED_I210 0x00080000
1249#define E1000_FLUDONE_ATTEMPTS 20000
1250#define E1000_EECD_AUPDEN 0x00100000
1251#define E1000_EECD_SHADV 0x00200000
1252#define E1000_EECD_SEC1VAL 0x00400000
1253#define E1000_EECD_SECVAL_SHIFT 22
1254#define E1000_STM_OPCODE 0xDB00
1255#define E1000_HICR_FW_RESET 0xC0
1256
1257#define E1000_SHADOW_RAM_WORDS 2048
1258#define E1000_ICH_NVM_SIG_WORD 0x13
1259#define E1000_ICH_NVM_SIG_MASK 0xC0
1260
1261
1262#define E1000_EERD_START 0x00000001
1263#define E1000_EERD_DONE 0x00000010
1264#define E1000_EERD_ADDR_SHIFT 8
1265#define E1000_EERD_ADDR_MASK 0x0000FF00
1266#define E1000_EERD_DATA_SHIFT 16
1267#define E1000_EERD_DATA_MASK 0xFFFF0000
1268
1269
1270#define EEPROM_READ_OPCODE_MICROWIRE 0x6
1271#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5
1272#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7
1273#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13
1274#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10
1275
1276
1277#define EEPROM_MAX_RETRY_SPI 5000
1278#define EEPROM_READ_OPCODE_SPI 0x03
1279#define EEPROM_WRITE_OPCODE_SPI 0x02
1280#define EEPROM_A8_OPCODE_SPI 0x08
1281#define EEPROM_WREN_OPCODE_SPI 0x06
1282#define EEPROM_WRDI_OPCODE_SPI 0x04
1283#define EEPROM_RDSR_OPCODE_SPI 0x05
1284#define EEPROM_WRSR_OPCODE_SPI 0x01
1285#define EEPROM_ERASE4K_OPCODE_SPI 0x20
1286#define EEPROM_ERASE64K_OPCODE_SPI 0xD8
1287#define EEPROM_ERASE256_OPCODE_SPI 0xDB
1288
1289
1290#define EEPROM_WORD_SIZE_SHIFT 6
1291#define EEPROM_SIZE_SHIFT 10
1292#define EEPROM_SIZE_MASK 0x1C00
1293
1294
1295#define EEPROM_COMPAT 0x0003
1296#define EEPROM_ID_LED_SETTINGS 0x0004
1297#define EEPROM_VERSION 0x0005
1298#define EEPROM_SERDES_AMPLITUDE 0x0006
1299
1300#define EEPROM_PHY_CLASS_WORD 0x0007
1301#define EEPROM_INIT_CONTROL1_REG 0x000A
1302#define EEPROM_INIT_CONTROL2_REG 0x000F
1303#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
1304#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1305#define EEPROM_INIT_3GIO_3 0x001A
1306#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
1307#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
1308#define EEPROM_CFG 0x0012
1309#define EEPROM_FLASH_VERSION 0x0032
1310#define EEPROM_CHECKSUM_REG 0x003F
1311
1312#define E1000_EEPROM_CFG_DONE 0x00040000
1313#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000
1314
1315
1316#define E1000_CTRL_EXT_GPI0_EN 0x00000001
1317#define E1000_CTRL_EXT_GPI1_EN 0x00000002
1318#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1319#define E1000_CTRL_EXT_GPI2_EN 0x00000004
1320#define E1000_CTRL_EXT_GPI3_EN 0x00000008
1321#define E1000_CTRL_EXT_SDP4_DATA 0x00000010
1322
1323#define E1000_CTRL_EXT_SDP5_DATA 0x00000020
1324
1325#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1326#define E1000_CTRL_EXT_SDP6_DATA 0x00000040
1327#define E1000_CTRL_EXT_SWDPIN6 0x00000040
1328#define E1000_CTRL_EXT_SDP7_DATA 0x00000080
1329#define E1000_CTRL_EXT_SWDPIN7 0x00000080
1330#define E1000_CTRL_EXT_SDP4_DIR 0x00000100
1331#define E1000_CTRL_EXT_SDP5_DIR 0x00000200
1332#define E1000_CTRL_EXT_SDP6_DIR 0x00000400
1333#define E1000_CTRL_EXT_SWDPIO6 0x00000400
1334#define E1000_CTRL_EXT_SDP7_DIR 0x00000800
1335#define E1000_CTRL_EXT_SWDPIO7 0x00000800
1336#define E1000_CTRL_EXT_ASDCHK 0x00001000
1337#define E1000_CTRL_EXT_EE_RST 0x00002000
1338#define E1000_CTRL_EXT_IPS 0x00004000
1339#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
1340#define E1000_CTRL_EXT_RO_DIS 0x00020000
1341#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1342#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1343#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1344#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1345#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1346#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1347#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1348#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1349
1350
1351#define E1000_MDIC_DATA_MASK 0x0000FFFF
1352#define E1000_MDIC_REG_MASK 0x001F0000
1353#define E1000_MDIC_REG_SHIFT 16
1354#define E1000_MDIC_PHY_MASK 0x03E00000
1355#define E1000_MDIC_PHY_SHIFT 21
1356#define E1000_MDIC_OP_WRITE 0x04000000
1357#define E1000_MDIC_OP_READ 0x08000000
1358#define E1000_MDIC_READY 0x10000000
1359#define E1000_MDIC_INT_EN 0x20000000
1360#define E1000_MDIC_ERROR 0x40000000
1361
1362#define E1000_PHY_CTRL_SPD_EN 0x00000001
1363#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1364#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1365#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1366#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1367#define E1000_PHY_CTRL_B2B_EN 0x00000080
1368
1369#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1370#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1371#define E1000_LEDCTL_LED0_IVRT 0x00000040
1372#define E1000_LEDCTL_LED0_BLINK 0x00000080
1373#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1374#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1375#define E1000_LEDCTL_LED1_IVRT 0x00004000
1376#define E1000_LEDCTL_LED1_BLINK 0x00008000
1377#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1378#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1379#define E1000_LEDCTL_LED2_IVRT 0x00400000
1380#define E1000_LEDCTL_LED2_BLINK 0x00800000
1381#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1382#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1383#define E1000_LEDCTL_LED3_IVRT 0x40000000
1384#define E1000_LEDCTL_LED3_BLINK 0x80000000
1385
1386#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1387#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1388#define E1000_LEDCTL_MODE_LINK_UP 0x2
1389#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1390#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1391#define E1000_LEDCTL_MODE_LINK_10 0x5
1392#define E1000_LEDCTL_MODE_LINK_100 0x6
1393#define E1000_LEDCTL_MODE_LINK_1000 0x7
1394#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1395#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1396#define E1000_LEDCTL_MODE_COLLISION 0xA
1397#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1398#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1399#define E1000_LEDCTL_MODE_PAUSED 0xD
1400#define E1000_LEDCTL_MODE_LED_ON 0xE
1401#define E1000_LEDCTL_MODE_LED_OFF 0xF
1402
1403
1404#define E1000_RAH_AV 0x80000000
1405
1406
1407#define E1000_ICR_TXDW 0x00000001
1408#define E1000_ICR_TXQE 0x00000002
1409#define E1000_ICR_LSC 0x00000004
1410#define E1000_ICR_RXSEQ 0x00000008
1411#define E1000_ICR_RXDMT0 0x00000010
1412#define E1000_ICR_RXO 0x00000040
1413#define E1000_ICR_RXT0 0x00000080
1414#define E1000_ICR_MDAC 0x00000200
1415#define E1000_ICR_RXCFG 0x00000400
1416#define E1000_ICR_GPI_EN0 0x00000800
1417#define E1000_ICR_GPI_EN1 0x00001000
1418#define E1000_ICR_GPI_EN2 0x00002000
1419#define E1000_ICR_GPI_EN3 0x00004000
1420#define E1000_ICR_TXD_LOW 0x00008000
1421#define E1000_ICR_SRPD 0x00010000
1422
1423
1424#define E1000_ICS_TXDW E1000_ICR_TXDW
1425#define E1000_ICS_TXQE E1000_ICR_TXQE
1426#define E1000_ICS_LSC E1000_ICR_LSC
1427#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
1428#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
1429#define E1000_ICS_RXO E1000_ICR_RXO
1430#define E1000_ICS_RXT0 E1000_ICR_RXT0
1431#define E1000_ICS_MDAC E1000_ICR_MDAC
1432#define E1000_ICS_RXCFG E1000_ICR_RXCFG
1433#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0
1434#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1
1435#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2
1436#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3
1437#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1438#define E1000_ICS_SRPD E1000_ICR_SRPD
1439
1440
1441#define E1000_IMS_TXDW E1000_ICR_TXDW
1442#define E1000_IMS_TXQE E1000_ICR_TXQE
1443#define E1000_IMS_LSC E1000_ICR_LSC
1444#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
1445#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
1446#define E1000_IMS_RXO E1000_ICR_RXO
1447#define E1000_IMS_RXT0 E1000_ICR_RXT0
1448#define E1000_IMS_MDAC E1000_ICR_MDAC
1449#define E1000_IMS_RXCFG E1000_ICR_RXCFG
1450#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0
1451#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1
1452#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2
1453#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3
1454#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1455#define E1000_IMS_SRPD E1000_ICR_SRPD
1456
1457
1458#define E1000_IMC_TXDW E1000_ICR_TXDW
1459#define E1000_IMC_TXQE E1000_ICR_TXQE
1460#define E1000_IMC_LSC E1000_ICR_LSC
1461#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ
1462#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0
1463#define E1000_IMC_RXO E1000_ICR_RXO
1464#define E1000_IMC_RXT0 E1000_ICR_RXT0
1465#define E1000_IMC_MDAC E1000_ICR_MDAC
1466#define E1000_IMC_RXCFG E1000_ICR_RXCFG
1467#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0
1468#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1
1469#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2
1470#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3
1471#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1472#define E1000_IMC_SRPD E1000_ICR_SRPD
1473
1474
1475#define E1000_RCTL_RST 0x00000001
1476#define E1000_RCTL_EN 0x00000002
1477#define E1000_RCTL_SBP 0x00000004
1478#define E1000_RCTL_UPE 0x00000008
1479#define E1000_RCTL_MPE 0x00000010
1480#define E1000_RCTL_LPE 0x00000020
1481#define E1000_RCTL_LBM_NO 0x00000000
1482#define E1000_RCTL_LBM_MAC 0x00000040
1483#define E1000_RCTL_LBM_SLP 0x00000080
1484#define E1000_RCTL_LBM_TCVR 0x000000C0
1485#define E1000_RCTL_RDMTS_HALF 0x00000000
1486#define E1000_RCTL_RDMTS_QUAT 0x00000100
1487#define E1000_RCTL_RDMTS_EIGTH 0x00000200
1488#define E1000_RCTL_MO_SHIFT 12
1489#define E1000_RCTL_MO_0 0x00000000
1490#define E1000_RCTL_MO_1 0x00001000
1491#define E1000_RCTL_MO_2 0x00002000
1492#define E1000_RCTL_MO_3 0x00003000
1493#define E1000_RCTL_MDR 0x00004000
1494#define E1000_RCTL_BAM 0x00008000
1495
1496#define E1000_RCTL_SZ_2048 0x00000000
1497#define E1000_RCTL_SZ_1024 0x00010000
1498#define E1000_RCTL_SZ_512 0x00020000
1499#define E1000_RCTL_SZ_256 0x00030000
1500
1501#define E1000_RCTL_SZ_16384 0x00010000
1502#define E1000_RCTL_SZ_8192 0x00020000
1503#define E1000_RCTL_SZ_4096 0x00030000
1504#define E1000_RCTL_VFE 0x00040000
1505#define E1000_RCTL_CFIEN 0x00080000
1506#define E1000_RCTL_CFI 0x00100000
1507#define E1000_RCTL_DPF 0x00400000
1508#define E1000_RCTL_PMCF 0x00800000
1509#define E1000_RCTL_BSEX 0x02000000
1510
1511
1512#define E1000_SWFW_EEP_SM 0x0001
1513#define E1000_SWFW_PHY0_SM 0x0002
1514#define E1000_SWFW_PHY1_SM 0x0004
1515#define E1000_SWFW_MAC_CSR_SM 0x0008
1516
1517
1518#define E1000_RDT_DELAY 0x0000ffff
1519#define E1000_RDT_FPDB 0x80000000
1520#define E1000_RDLEN_LEN 0x0007ff80
1521#define E1000_RDH_RDH 0x0000ffff
1522#define E1000_RDT_RDT 0x0000ffff
1523
1524
1525#define E1000_FCRTH_RTH 0x0000FFF8
1526#define E1000_FCRTH_XFCE 0x80000000
1527#define E1000_FCRTL_RTL 0x0000FFF8
1528#define E1000_FCRTL_XONE 0x80000000
1529
1530
1531#define E1000_RXDCTL_PTHRESH 0x0000003F
1532#define E1000_RXDCTL_HTHRESH 0x00003F00
1533#define E1000_RXDCTL_WTHRESH 0x003F0000
1534#define E1000_RXDCTL_GRAN 0x01000000
1535#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000
1536
1537
1538#define E1000_TXDCTL_PTHRESH 0x0000003F
1539#define E1000_TXDCTL_HTHRESH 0x00003F00
1540#define E1000_TXDCTL_WTHRESH 0x003F0000
1541#define E1000_TXDCTL_GRAN 0x01000000
1542#define E1000_TXDCTL_LWTHRESH 0xFE000000
1543#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
1544#define E1000_TXDCTL_COUNT_DESC 0x00400000
1545
1546
1547
1548#define E1000_TXCW_FD 0x00000020
1549#define E1000_TXCW_HD 0x00000040
1550#define E1000_TXCW_PAUSE 0x00000080
1551#define E1000_TXCW_ASM_DIR 0x00000100
1552#define E1000_TXCW_PAUSE_MASK 0x00000180
1553#define E1000_TXCW_RF 0x00003000
1554#define E1000_TXCW_NP 0x00008000
1555#define E1000_TXCW_CW 0x0000ffff
1556#define E1000_TXCW_TXC 0x40000000
1557#define E1000_TXCW_ANE 0x80000000
1558
1559
1560#define E1000_RXCW_CW 0x0000ffff
1561#define E1000_RXCW_NC 0x04000000
1562#define E1000_RXCW_IV 0x08000000
1563#define E1000_RXCW_CC 0x10000000
1564#define E1000_RXCW_C 0x20000000
1565#define E1000_RXCW_SYNCH 0x40000000
1566#define E1000_RXCW_ANC 0x80000000
1567
1568
1569#define E1000_TCTL_RST 0x00000001
1570#define E1000_TCTL_EN 0x00000002
1571#define E1000_TCTL_BCE 0x00000004
1572#define E1000_TCTL_PSP 0x00000008
1573#define E1000_TCTL_CT 0x00000ff0
1574#define E1000_TCTL_COLD 0x003ff000
1575#define E1000_TCTL_SWXOFF 0x00400000
1576#define E1000_TCTL_PBE 0x00800000
1577#define E1000_TCTL_RTLC 0x01000000
1578#define E1000_TCTL_NRTU 0x02000000
1579#define E1000_TCTL_MULR 0x10000000
1580
1581
1582#define E1000_RXCSUM_PCSS_MASK 0x000000FF
1583#define E1000_RXCSUM_IPOFL 0x00000100
1584#define E1000_RXCSUM_TUOFL 0x00000200
1585#define E1000_RXCSUM_IPV6OFL 0x00000400
1586
1587
1588
1589#define E1000_WUC_APME 0x00000001
1590#define E1000_WUC_PME_EN 0x00000002
1591#define E1000_WUC_PME_STATUS 0x00000004
1592#define E1000_WUC_APMPME 0x00000008
1593
1594
1595#define E1000_WUFC_LNKC 0x00000001
1596#define E1000_WUFC_MAG 0x00000002
1597#define E1000_WUFC_EX 0x00000004
1598#define E1000_WUFC_MC 0x00000008
1599#define E1000_WUFC_BC 0x00000010
1600#define E1000_WUFC_ARP 0x00000020
1601#define E1000_WUFC_IPV4 0x00000040
1602#define E1000_WUFC_IPV6 0x00000080
1603#define E1000_WUFC_FLX0 0x00010000
1604#define E1000_WUFC_FLX1 0x00020000
1605#define E1000_WUFC_FLX2 0x00040000
1606#define E1000_WUFC_FLX3 0x00080000
1607#define E1000_WUFC_ALL_FILTERS 0x000F00FF
1608#define E1000_WUFC_FLX_OFFSET 16
1609#define E1000_WUFC_FLX_FILTERS 0x000F0000
1610
1611
1612#define E1000_WUS_LNKC 0x00000001
1613#define E1000_WUS_MAG 0x00000002
1614#define E1000_WUS_EX 0x00000004
1615#define E1000_WUS_MC 0x00000008
1616#define E1000_WUS_BC 0x00000010
1617#define E1000_WUS_ARP 0x00000020
1618#define E1000_WUS_IPV4 0x00000040
1619#define E1000_WUS_IPV6 0x00000080
1620#define E1000_WUS_FLX0 0x00010000
1621#define E1000_WUS_FLX1 0x00020000
1622#define E1000_WUS_FLX2 0x00040000
1623#define E1000_WUS_FLX3 0x00080000
1624#define E1000_WUS_FLX_FILTERS 0x000F0000
1625
1626
1627#define E1000_MANC_SMBUS_EN 0x00000001
1628#define E1000_MANC_ASF_EN 0x00000002
1629#define E1000_MANC_R_ON_FORCE 0x00000004
1630#define E1000_MANC_RMCP_EN 0x00000100
1631#define E1000_MANC_0298_EN 0x00000200
1632#define E1000_MANC_IPV4_EN 0x00000400
1633#define E1000_MANC_IPV6_EN 0x00000800
1634#define E1000_MANC_SNAP_EN 0x00001000
1635#define E1000_MANC_ARP_EN 0x00002000
1636#define E1000_MANC_NEIGHBOR_EN 0x00004000
1637
1638#define E1000_MANC_TCO_RESET 0x00010000
1639#define E1000_MANC_RCV_TCO_EN 0x00020000
1640#define E1000_MANC_REPORT_STATUS 0x00040000
1641#define E1000_MANC_SMB_REQ 0x01000000
1642#define E1000_MANC_SMB_GNT 0x02000000
1643#define E1000_MANC_SMB_CLK_IN 0x04000000
1644#define E1000_MANC_SMB_DATA_IN 0x08000000
1645#define E1000_MANC_SMB_DATA_OUT 0x10000000
1646#define E1000_MANC_SMB_CLK_OUT 0x20000000
1647
1648#define E1000_MANC_SMB_DATA_OUT_SHIFT 28
1649#define E1000_MANC_SMB_CLK_OUT_SHIFT 29
1650
1651
1652#define E1000_WUPL_LENGTH_MASK 0x0FFF
1653
1654#define E1000_MDALIGN 4096
1655
1656
1657#define EEPROM_READ_OPCODE 0x6
1658#define EEPROM_WRITE_OPCODE 0x5
1659#define EEPROM_ERASE_OPCODE 0x7
1660#define EEPROM_EWEN_OPCODE 0x13
1661#define EEPROM_EWDS_OPCODE 0x10
1662
1663
1664#define ID_LED_RESERVED_0000 0x0000
1665#define ID_LED_RESERVED_FFFF 0xFFFF
1666#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1667 (ID_LED_OFF1_OFF2 << 8) | \
1668 (ID_LED_DEF1_DEF2 << 4) | \
1669 (ID_LED_DEF1_DEF2))
1670#define ID_LED_DEF1_DEF2 0x1
1671#define ID_LED_DEF1_ON2 0x2
1672#define ID_LED_DEF1_OFF2 0x3
1673#define ID_LED_ON1_DEF2 0x4
1674#define ID_LED_ON1_ON2 0x5
1675#define ID_LED_ON1_OFF2 0x6
1676#define ID_LED_OFF1_DEF2 0x7
1677#define ID_LED_OFF1_ON2 0x8
1678#define ID_LED_OFF1_OFF2 0x9
1679
1680
1681#define EEPROM_COMPAT_SERVER 0x0400
1682#define EEPROM_COMPAT_CLIENT 0x0200
1683
1684
1685#define EEPROM_WORD0A_ILOS 0x0010
1686#define EEPROM_WORD0A_SWDPIO 0x01E0
1687#define EEPROM_WORD0A_LRST 0x0200
1688#define EEPROM_WORD0A_FD 0x0400
1689#define EEPROM_WORD0A_66MHZ 0x0800
1690
1691
1692#define EEPROM_WORD0F_PAUSE_MASK 0x3000
1693#define EEPROM_WORD0F_PAUSE 0x1000
1694#define EEPROM_WORD0F_ASM_DIR 0x2000
1695#define EEPROM_WORD0F_ANE 0x0800
1696#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1697
1698
1699#define EEPROM_SUM 0xBABA
1700
1701
1702#define EEPROM_NODE_ADDRESS_BYTE_0 0
1703#define EEPROM_PBA_BYTE_1 8
1704
1705
1706#define PBA_SIZE 4
1707
1708
1709#define E1000_COLLISION_THRESHOLD 0xF
1710#define E1000_CT_SHIFT 4
1711#define E1000_COLLISION_DISTANCE 63
1712#define E1000_COLLISION_DISTANCE_82542 64
1713#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1714#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1715#define E1000_GB_HDX_COLLISION_DISTANCE 512
1716#define E1000_COLD_SHIFT 12
1717
1718
1719#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1720#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1721
1722
1723#define DEFAULT_82542_TIPG_IPGT 10
1724#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1725#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1726
1727#define E1000_TIPG_IPGT_MASK 0x000003FF
1728#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1729#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1730
1731#define DEFAULT_82542_TIPG_IPGR1 2
1732#define DEFAULT_82543_TIPG_IPGR1 8
1733#define E1000_TIPG_IPGR1_SHIFT 10
1734
1735#define DEFAULT_82542_TIPG_IPGR2 10
1736#define DEFAULT_82543_TIPG_IPGR2 6
1737#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
1738#define E1000_TIPG_IPGR2_SHIFT 20
1739
1740#define E1000_TXDMAC_DPP 0x00000001
1741
1742
1743#define TX_THRESHOLD_START 8
1744#define TX_THRESHOLD_INCREMENT 10
1745#define TX_THRESHOLD_DECREMENT 1
1746#define TX_THRESHOLD_STOP 190
1747#define TX_THRESHOLD_DISABLE 0
1748#define TX_THRESHOLD_TIMER_MS 10000
1749#define MIN_NUM_XMITS 1000
1750#define IFS_MAX 80
1751#define IFS_STEP 10
1752#define IFS_MIN 40
1753#define IFS_RATIO 4
1754
1755
1756#define E1000_PBA_16K 0x0010
1757#define E1000_PBA_24K 0x0018
1758#define E1000_PBA_38K 0x0026
1759#define E1000_PBA_40K 0x0028
1760#define E1000_PBA_48K 0x0030
1761
1762
1763#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1764#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1765#define FLOW_CONTROL_TYPE 0x8808
1766
1767
1768#define FC_DEFAULT_HI_THRESH (0x8000)
1769#define FC_DEFAULT_LO_THRESH (0x4000)
1770#define FC_DEFAULT_TX_TIMER (0x100)
1771
1772
1773#define E1000_FC_HIGH_THRESH 0xA9C8
1774
1775#define E1000_FC_LOW_THRESH 0xA9C0
1776
1777#define E1000_FC_PAUSE_TIME 0x0680
1778
1779
1780#define PCIX_COMMAND_REGISTER 0xE6
1781#define PCIX_STATUS_REGISTER_LO 0xE8
1782#define PCIX_STATUS_REGISTER_HI 0xEA
1783
1784#define PCIX_COMMAND_MMRBC_MASK 0x000C
1785#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1786#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1787#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1788#define PCIX_STATUS_HI_MMRBC_4K 0x3
1789#define PCIX_STATUS_HI_MMRBC_2K 0x2
1790
1791
1792
1793
1794
1795#define PAUSE_SHIFT 5
1796
1797
1798
1799
1800
1801#define SWDPIO_SHIFT 17
1802
1803
1804
1805
1806
1807
1808#define SWDPIO__EXT_SHIFT 4
1809
1810
1811
1812
1813
1814#define ILOS_SHIFT 3
1815
1816#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1817
1818
1819#define LINK_UP_TIMEOUT 500
1820
1821#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1822
1823
1824#define CARRIER_EXTENSION 0x0F
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1854 ((adapter)->tbi_compatibility_on && \
1855 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1856 ((last_byte) == CARRIER_EXTENSION) && \
1857 (((status) & E1000_RXD_STAT_VP) ? \
1858 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1859 ((length) <= ((adapter)->max_frame_size + 1))) : \
1860 (((length) > (adapter)->min_frame_size) && \
1861 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1862
1863
1864
1865
1866
1867
1868#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1869#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1870#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1871#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1872#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1873#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1874#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1875#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1876
1877
1878
1879#define PHY_CTRL 0x00
1880#define PHY_STATUS 0x01
1881#define PHY_ID1 0x02
1882#define PHY_ID2 0x03
1883#define PHY_AUTONEG_ADV 0x04
1884#define PHY_LP_ABILITY 0x05
1885#define PHY_AUTONEG_EXP 0x06
1886#define PHY_NEXT_PAGE_TX 0x07
1887#define PHY_LP_NEXT_PAGE 0x08
1888#define PHY_1000T_CTRL 0x09
1889#define PHY_1000T_STATUS 0x0A
1890#define PHY_EXT_STATUS 0x0F
1891
1892
1893#define M88E1000_PHY_SPEC_CTRL 0x10
1894#define M88E1000_PHY_SPEC_STATUS 0x11
1895#define M88E1000_INT_ENABLE 0x12
1896#define M88E1000_INT_STATUS 0x13
1897#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
1898#define M88E1000_RX_ERR_CNTR 0x15
1899
1900#define M88E1000_PHY_PAGE_SELECT 0x1D
1901#define M88E1000_PHY_GEN_CONTROL 0x1E
1902
1903#define MAX_PHY_REG_ADDRESS 0x1F
1904
1905
1906#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1907#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1908#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1909#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1910#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1911#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1912#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1913#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1914#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1915
1916
1917#define IGP01E1000_IEEE_REGS_PAGE 0x0000
1918#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1919#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
1920
1921
1922#define IGP01E1000_PHY_PORT_CONFIG 0x10
1923#define IGP01E1000_PHY_PORT_STATUS 0x11
1924#define IGP01E1000_PHY_PORT_CTRL 0x12
1925#define IGP01E1000_PHY_LINK_HEALTH 0x13
1926#define IGP01E1000_GMII_FIFO 0x14
1927#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15
1928#define IGP02E1000_PHY_POWER_MGMT 0x19
1929#define IGP01E1000_PHY_PAGE_SELECT 0x1F
1930
1931
1932#define IGP01E1000_PHY_AGC_A 0x1172
1933#define IGP01E1000_PHY_AGC_B 0x1272
1934#define IGP01E1000_PHY_AGC_C 0x1472
1935#define IGP01E1000_PHY_AGC_D 0x1872
1936
1937
1938#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
1939#define IGP01E1000_PSCFR_PRE_EN 0x0020
1940#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
1941#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
1942#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
1943#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
1944
1945#define IGP02E1000_PHY_AGC_A 0x11B1
1946#define IGP02E1000_PHY_AGC_B 0x12B1
1947#define IGP02E1000_PHY_AGC_C 0x14B1
1948#define IGP02E1000_PHY_AGC_D 0x18B1
1949
1950#define IGP02E1000_PM_SPD 0x0001
1951#define IGP02E1000_PM_D3_LPLU 0x0004
1952
1953#define IGP02E1000_PM_D0_LPLU 0x0002
1954
1955
1956
1957#define IGP01E1000_PHY_DSP_RESET 0x1F33
1958#define IGP01E1000_PHY_DSP_SET 0x1F71
1959#define IGP01E1000_PHY_DSP_FFE 0x1F35
1960
1961#define IGP01E1000_PHY_CHANNEL_NUM 4
1962#define IGP02E1000_PHY_CHANNEL_NUM 4
1963
1964#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1965#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1966#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
1967#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
1968
1969#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
1970#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
1971
1972#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
1973#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
1974#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
1975#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
1976
1977#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
1978
1979
1980#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
1981#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
1982
1983#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
1984
1985
1986#define IGP01E1000_GMII_FLEX_SPD 0x10
1987
1988#define IGP01E1000_GMII_SPD 0x20
1989
1990
1991#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
1992#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
1993#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
1994#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
1995
1996#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
1997#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
1998#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
1999#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2000#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2001
2002#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2003#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2004#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2005#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2006
2007
2008#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2009#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2010#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2011#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2012#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2013#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000
2014
2015#define GG82563_PSCR_DISABLE_JABBER 0x0001
2016#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002
2017
2018#define GG82563_PSCR_POWER_DOWN 0x0004
2019#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008
2020
2021#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2022#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000
2023
2024#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020
2025
2026#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060
2027
2028#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080
2029
2030#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
2031#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000
2032#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200
2033
2034#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300
2035#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400
2036#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800
2037#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
2038#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
2039
2040
2041#define GG82563_PSSR_JABBER 0x0001
2042#define GG82563_PSSR_POLARITY 0x0002
2043#define GG82563_PSSR_LINK 0x0008
2044#define GG82563_PSSR_ENERGY_DETECT 0x0010
2045#define GG82563_PSSR_DOWNSHIFT 0x0020
2046#define GG82563_PSSR_CROSSOVER_STATUS 0x0040
2047#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100
2048#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200
2049#define GG82563_PSSR_LINK_UP 0x0400
2050#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800
2051#define GG82563_PSSR_PAGE_RECEIVED 0x1000
2052#define GG82563_PSSR_DUPLEX 0x2000
2053#define GG82563_PSSR_SPEED_MASK 0xC000
2054#define GG82563_PSSR_SPEED_10MBPS 0x0000
2055#define GG82563_PSSR_SPEED_100MBPS 0x4000
2056#define GG82563_PSSR_SPEED_1000MBPS 0x8000
2057
2058
2059#define GG82563_PSSR2_JABBER 0x0001
2060#define GG82563_PSSR2_POLARITY_CHANGED 0x0002
2061#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010
2062#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020
2063#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040
2064#define GG82563_PSSR2_FALSE_CARRIER 0x0100
2065#define GG82563_PSSR2_SYMBOL_ERROR 0x0200
2066#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400
2067#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800
2068#define GG82563_PSSR2_PAGE_RECEIVED 0x1000
2069#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000
2070#define GG82563_PSSR2_SPEED_CHANGED 0x4000
2071#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000
2072
2073
2074#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002
2075
2076#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
2077#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000
2078
2079#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008
2080
2081#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C
2082
2083#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
2084
2085#define GG82563_PSCR2_1000BT_DISABLE 0x4000
2086
2087#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
2088#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000
2089#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000
2090
2091
2092
2093#define GG82563_MSCR_TX_CLK_MASK 0x0007
2094#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
2095#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
2096#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
2097#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
2098
2099#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010
2100
2101
2102#define GG82563_DSPD_CABLE_LENGTH 0x0007
2103
2104
2105
2106
2107
2108
2109#define GG82563_KMCR_PHY_LEDS_EN 0x0020
2110
2111#define GG82563_KMCR_FORCE_LINK_UP 0x0040
2112#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
2113#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
2114#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400
2115
2116#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2117
2118
2119#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
2120
2121#define GG82563_PMCR_DISABLE_PORT 0x0002
2122#define GG82563_PMCR_DISABLE_SERDES 0x0004
2123#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008
2124
2125#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010
2126
2127#define GG82563_PMCR_DISABLE_1000 0x0020
2128
2129#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040
2130
2131#define GG82563_PMCR_FORCE_POWER_STATE 0x0080
2132#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
2133#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000
2134#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100
2135#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200
2136#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300
2137
2138
2139#define GG82563_ICR_DIS_PADDING 0x0010
2140
2141
2142
2143
2144
2145
2146#define GG82563_PAGE_SHIFT 5
2147#define GG82563_REG(page, reg) \
2148 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2149#define GG82563_MIN_ALT_REG 30
2150
2151
2152#define GG82563_PHY_SPEC_CTRL \
2153 GG82563_REG(0, 16)
2154#define GG82563_PHY_SPEC_STATUS \
2155 GG82563_REG(0, 17)
2156#define GG82563_PHY_INT_ENABLE \
2157 GG82563_REG(0, 18)
2158#define GG82563_PHY_SPEC_STATUS_2 \
2159 GG82563_REG(0, 19)
2160#define GG82563_PHY_RX_ERR_CNTR \
2161 GG82563_REG(0, 21)
2162#define GG82563_PHY_PAGE_SELECT \
2163 GG82563_REG(0, 22)
2164#define GG82563_PHY_SPEC_CTRL_2 \
2165 GG82563_REG(0, 26)
2166#define GG82563_PHY_PAGE_SELECT_ALT \
2167 GG82563_REG(0, 29)
2168#define GG82563_PHY_TEST_CLK_CTRL \
2169 GG82563_REG(0, 30)
2170
2171#define GG82563_PHY_MAC_SPEC_CTRL \
2172 GG82563_REG(2, 21)
2173#define GG82563_PHY_MAC_SPEC_CTRL_2 \
2174 GG82563_REG(2, 26)
2175
2176#define GG82563_PHY_DSP_DISTANCE \
2177 GG82563_REG(5, 26)
2178
2179
2180#define GG82563_PHY_KMRN_MODE_CTRL \
2181 GG82563_REG(193, 16)
2182#define GG82563_PHY_PORT_RESET \
2183 GG82563_REG(193, 17)
2184#define GG82563_PHY_REVISION_ID \
2185 GG82563_REG(193, 18)
2186#define GG82563_PHY_DEVICE_ID \
2187 GG82563_REG(193, 19)
2188#define GG82563_PHY_PWR_MGMT_CTRL \
2189 GG82563_REG(193, 20)
2190#define GG82563_PHY_RATE_ADAPT_CTRL \
2191 GG82563_REG(193, 25)
2192
2193
2194#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2195 GG82563_REG(194, 16)
2196#define GG82563_PHY_KMRN_CTRL \
2197 GG82563_REG(194, 17)
2198#define GG82563_PHY_INBAND_CTRL \
2199 GG82563_REG(194, 18)
2200#define GG82563_PHY_KMRN_DIAGNOSTIC \
2201 GG82563_REG(194, 19)
2202#define GG82563_PHY_ACK_TIMEOUTS \
2203 GG82563_REG(194, 20)
2204#define GG82563_PHY_ADV_ABILITY \
2205 GG82563_REG(194, 21)
2206#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2207 GG82563_REG(194, 23)
2208#define GG82563_PHY_ADV_NEXT_PAGE \
2209 GG82563_REG(194, 24)
2210#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2211 GG82563_REG(194, 25)
2212#define GG82563_PHY_KMRN_MISC \
2213 GG82563_REG(194, 26)
2214
2215
2216#define MII_CR_SPEED_SELECT_MSB 0x0040
2217#define MII_CR_COLL_TEST_ENABLE 0x0080
2218#define MII_CR_FULL_DUPLEX 0x0100
2219#define MII_CR_RESTART_AUTO_NEG 0x0200
2220#define MII_CR_ISOLATE 0x0400
2221#define MII_CR_POWER_DOWN 0x0800
2222#define MII_CR_AUTO_NEG_EN 0x1000
2223#define MII_CR_SPEED_SELECT_LSB 0x2000
2224#define MII_CR_LOOPBACK 0x4000
2225#define MII_CR_RESET 0x8000
2226
2227
2228#define MII_SR_EXTENDED_CAPS 0x0001
2229#define MII_SR_JABBER_DETECT 0x0002
2230#define MII_SR_LINK_STATUS 0x0004
2231#define MII_SR_AUTONEG_CAPS 0x0008
2232#define MII_SR_REMOTE_FAULT 0x0010
2233#define MII_SR_AUTONEG_COMPLETE 0x0020
2234#define MII_SR_PREAMBLE_SUPPRESS 0x0040
2235#define MII_SR_EXTENDED_STATUS 0x0100
2236#define MII_SR_100T2_HD_CAPS 0x0200
2237#define MII_SR_100T2_FD_CAPS 0x0400
2238#define MII_SR_10T_HD_CAPS 0x0800
2239#define MII_SR_10T_FD_CAPS 0x1000
2240#define MII_SR_100X_HD_CAPS 0x2000
2241#define MII_SR_100X_FD_CAPS 0x4000
2242#define MII_SR_100T4_CAPS 0x8000
2243
2244
2245#define NWAY_AR_SELECTOR_FIELD 0x0001
2246#define NWAY_AR_10T_HD_CAPS 0x0020
2247#define NWAY_AR_10T_FD_CAPS 0x0040
2248#define NWAY_AR_100TX_HD_CAPS 0x0080
2249#define NWAY_AR_100TX_FD_CAPS 0x0100
2250#define NWAY_AR_100T4_CAPS 0x0200
2251#define NWAY_AR_PAUSE 0x0400
2252#define NWAY_AR_ASM_DIR 0x0800
2253#define NWAY_AR_REMOTE_FAULT 0x2000
2254#define NWAY_AR_NEXT_PAGE 0x8000
2255
2256
2257#define NWAY_LPAR_SELECTOR_FIELD 0x0000
2258#define NWAY_LPAR_10T_HD_CAPS 0x0020
2259#define NWAY_LPAR_10T_FD_CAPS 0x0040
2260#define NWAY_LPAR_100TX_HD_CAPS 0x0080
2261#define NWAY_LPAR_100TX_FD_CAPS 0x0100
2262#define NWAY_LPAR_100T4_CAPS 0x0200
2263#define NWAY_LPAR_PAUSE 0x0400
2264#define NWAY_LPAR_ASM_DIR 0x0800
2265#define NWAY_LPAR_REMOTE_FAULT 0x2000
2266#define NWAY_LPAR_ACKNOWLEDGE 0x4000
2267#define NWAY_LPAR_NEXT_PAGE 0x8000
2268
2269
2270#define NWAY_ER_LP_NWAY_CAPS 0x0001
2271#define NWAY_ER_PAGE_RXD 0x0002
2272#define NWAY_ER_NEXT_PAGE_CAPS 0x0004
2273#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008
2274#define NWAY_ER_PAR_DETECT_FAULT 0x0100
2275
2276
2277#define NPTX_MSG_CODE_FIELD 0x0001
2278#define NPTX_TOGGLE 0x0800
2279
2280
2281#define NPTX_ACKNOWLDGE2 0x1000
2282
2283
2284#define NPTX_MSG_PAGE 0x2000
2285#define NPTX_NEXT_PAGE 0x8000
2286
2287
2288
2289
2290#define LP_RNPR_MSG_CODE_FIELD 0x0001
2291#define LP_RNPR_TOGGLE 0x0800
2292
2293
2294#define LP_RNPR_ACKNOWLDGE2 0x1000
2295
2296
2297#define LP_RNPR_MSG_PAGE 0x2000
2298#define LP_RNPR_ACKNOWLDGE 0x4000
2299#define LP_RNPR_NEXT_PAGE 0x8000
2300
2301
2302
2303
2304#define CR_1000T_ASYM_PAUSE 0x0080
2305#define CR_1000T_HD_CAPS 0x0100
2306#define CR_1000T_FD_CAPS 0x0200
2307#define CR_1000T_REPEATER_DTE 0x0400
2308
2309#define CR_1000T_MS_VALUE 0x0800
2310
2311#define CR_1000T_MS_ENABLE 0x1000
2312
2313#define CR_1000T_TEST_MODE_NORMAL 0x0000
2314#define CR_1000T_TEST_MODE_1 0x2000
2315#define CR_1000T_TEST_MODE_2 0x4000
2316#define CR_1000T_TEST_MODE_3 0x6000
2317#define CR_1000T_TEST_MODE_4 0x8000
2318
2319
2320#define SR_1000T_IDLE_ERROR_CNT 0x00FF
2321#define SR_1000T_ASYM_PAUSE_DIR 0x0100
2322#define SR_1000T_LP_HD_CAPS 0x0400
2323#define SR_1000T_LP_FD_CAPS 0x0800
2324#define SR_1000T_REMOTE_RX_STATUS 0x1000
2325#define SR_1000T_LOCAL_RX_STATUS 0x2000
2326#define SR_1000T_MS_CONFIG_RES 0x4000
2327#define SR_1000T_MS_CONFIG_FAULT 0x8000
2328#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2329#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2330
2331
2332#define IEEE_ESR_1000T_HD_CAPS 0x1000
2333#define IEEE_ESR_1000T_FD_CAPS 0x2000
2334#define IEEE_ESR_1000X_HD_CAPS 0x4000
2335#define IEEE_ESR_1000X_FD_CAPS 0x8000
2336
2337#define PHY_TX_POLARITY_MASK 0x0100
2338#define PHY_TX_NORMAL_POLARITY 0
2339
2340#define AUTO_POLARITY_DISABLE 0x0010
2341
2342
2343
2344#define M88E1000_PSCR_JABBER_DISABLE 0x0001
2345#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
2346#define M88E1000_PSCR_SQE_TEST 0x0004
2347#define M88E1000_PSCR_CLK125_DISABLE 0x0010
2348
2349
2350#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
2351
2352#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
2353#define M88E1000_PSCR_AUTO_X_1000T 0x0040
2354
2355
2356
2357#define M88E1000_PSCR_AUTO_X_MODE 0x0060
2358
2359
2360#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2361
2362
2363
2364#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2365
2366
2367#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200
2368#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400
2369#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
2370
2371#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2372#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2373#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2374
2375
2376#define M88E1000_PSSR_JABBER 0x0001
2377#define M88E1000_PSSR_REV_POLARITY 0x0002
2378#define M88E1000_PSSR_MDIX 0x0040
2379#define M88E1000_PSSR_CABLE_LENGTH 0x0380
2380
2381#define M88E1000_PSSR_LINK 0x0400
2382#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800
2383#define M88E1000_PSSR_PAGE_RCVD 0x1000
2384#define M88E1000_PSSR_DPLX 0x2000
2385#define M88E1000_PSSR_SPEED 0xC000
2386#define M88E1000_PSSR_10MBS 0x0000
2387#define M88E1000_PSSR_100MBS 0x4000
2388#define M88E1000_PSSR_1000MBS 0x8000
2389
2390#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2391#define M88E1000_PSSR_MDIX_SHIFT 6
2392#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2393
2394
2395#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000
2396#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
2397
2398
2399
2400
2401
2402
2403#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2404#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2405#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2406#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2407#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2408
2409
2410#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2411#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2412#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2413#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2414#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2415#define M88E1000_EPSCR_TX_CLK_2_5 0x0060
2416#define M88E1000_EPSCR_TX_CLK_25 0x0070
2417#define M88E1000_EPSCR_TX_CLK_0 0x0000
2418
2419
2420#define M88E1000_E_PHY_ID 0x01410C50
2421#define M88E1000_I_PHY_ID 0x01410C30
2422#define M88E1011_I_PHY_ID 0x01410C20
2423#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2424#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2425#define IGP01E1000_I_PHY_ID 0x02A80380
2426#define M88E1011_I_REV_4 0x04
2427#define M88E1111_I_PHY_ID 0x01410CC0
2428#define L1LXT971A_PHY_ID 0x001378E0
2429#define GG82563_E_PHY_ID 0x01410CA0
2430
2431#define BME1000_E_PHY_ID 0x01410CB0
2432
2433#define I210_I_PHY_ID 0x01410C00
2434
2435
2436#define PHY_PREAMBLE 0xFFFFFFFF
2437#define PHY_SOF 0x01
2438#define PHY_OP_READ 0x02
2439#define PHY_OP_WRITE 0x01
2440#define PHY_TURNAROUND 0x02
2441#define PHY_PREAMBLE_SIZE 32
2442#define MII_CR_SPEED_1000 0x0040
2443#define MII_CR_SPEED_100 0x2000
2444#define MII_CR_SPEED_10 0x0000
2445#define E1000_PHY_ADDRESS 0x01
2446#define PHY_AUTO_NEG_TIME 80
2447#define PHY_FORCE_TIME 20
2448#define PHY_REVISION_MASK 0xFFFFFFF0
2449#define DEVICE_SPEED_MASK 0x00000300
2450#define REG4_SPEED_MASK 0x01E0
2451#define REG9_SPEED_MASK 0x0300
2452#define ADVERTISE_10_HALF 0x0001
2453#define ADVERTISE_10_FULL 0x0002
2454#define ADVERTISE_100_HALF 0x0004
2455#define ADVERTISE_100_FULL 0x0008
2456#define ADVERTISE_1000_HALF 0x0010
2457#define ADVERTISE_1000_FULL 0x0020
2458
2459#define ICH_FLASH_GFPREG 0x0000
2460#define ICH_FLASH_HSFSTS 0x0004
2461#define ICH_FLASH_HSFCTL 0x0006
2462#define ICH_FLASH_FADDR 0x0008
2463#define ICH_FLASH_FDATA0 0x0010
2464#define ICH_FLASH_FRACC 0x0050
2465#define ICH_FLASH_FREG0 0x0054
2466#define ICH_FLASH_FREG1 0x0058
2467#define ICH_FLASH_FREG2 0x005C
2468#define ICH_FLASH_FREG3 0x0060
2469#define ICH_FLASH_FPR0 0x0074
2470#define ICH_FLASH_FPR1 0x0078
2471#define ICH_FLASH_SSFSTS 0x0090
2472#define ICH_FLASH_SSFCTL 0x0092
2473#define ICH_FLASH_PREOP 0x0094
2474#define ICH_FLASH_OPTYPE 0x0096
2475#define ICH_FLASH_OPMENU 0x0098
2476
2477#define ICH_FLASH_REG_MAPSIZE 0x00A0
2478#define ICH_FLASH_SECTOR_SIZE 4096
2479#define ICH_GFPREG_BASE_MASK 0x1FFF
2480#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
2481
2482#define E1000_SW_FW_SYNC 0x05B5C
2483
2484
2485#define EEPROM_STATUS_RDY_SPI 0x01
2486#define EEPROM_STATUS_WEN_SPI 0x02
2487#define EEPROM_STATUS_BP0_SPI 0x04
2488#define EEPROM_STATUS_BP1_SPI 0x08
2489#define EEPROM_STATUS_WPEN_SPI 0x80
2490
2491
2492#define E1000_SWSM_SMBI 0x00000001
2493#define E1000_SWSM_SWESMBI 0x00000002
2494#define E1000_SWSM_WMNG 0x00000004
2495#define E1000_SWSM_DRV_LOAD 0x00000008
2496
2497
2498#define E1000_FWSM_MODE_MASK 0x0000000E
2499#define E1000_FWSM_MODE_SHIFT 1
2500#define E1000_FWSM_FW_VALID 0x00008000
2501
2502#define E1000_FWSM_RSPCIPHY 0x00000040
2503#define E1000_FWSM_DISSW 0x10000000
2504#define E1000_FWSM_SKUSEL_MASK 0x60000000
2505#define E1000_FWSM_SKUEL_SHIFT 29
2506#define E1000_FWSM_SKUSEL_EMB 0x0
2507#define E1000_FWSM_SKUSEL_CONS 0x1
2508#define E1000_FWSM_SKUSEL_PERF_100 0x2
2509#define E1000_FWSM_SKUSEL_PERF_GBE 0x3
2510
2511#define E1000_GCR 0x05B00
2512#define E1000_GSCL_1 0x05B10
2513#define E1000_GSCL_2 0x05B14
2514#define E1000_GSCL_3 0x05B18
2515#define E1000_GSCL_4 0x05B1C
2516#define E1000_FACTPS 0x05B30
2517#define E1000_SWSM 0x05B50
2518#define E1000_FWSM 0x05B54
2519#define E1000_FFLT_DBG 0x05F04
2520#define E1000_HICR 0x08F00
2521
2522#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2523#define IGP_ACTIVITY_LED_ENABLE 0x0300
2524#define IGP_LED3_MODE 0x07000000
2525
2526
2527#define EEPROM_PHY_CLASS_A 0x8000
2528#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F
2529#define AUTONEG_ADVERTISE_10_100_ALL 0x000F
2530#define AUTONEG_ADVERTISE_10_ALL 0x0003
2531
2532#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
2533#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
2534#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
2535#define E1000_KUMCTRLSTA_REN 0x00200000
2536
2537#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
2538#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
2539#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
2540#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
2541#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
2542#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
2543#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
2544#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
2545#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
2546
2547
2548#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
2549#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
2550
2551
2552#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
2553#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
2554
2555
2556#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
2557#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
2558
2559#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
2560
2561#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
2562#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
2563
2564#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
2565#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
2566#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
2567
2568#define E1000_MNG_ICH_IAMT_MODE 0x2
2569#define E1000_MNG_IAMT_MODE 0x3
2570#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
2571#define E1000_KUMCTRLSTA 0x00034
2572
2573#define PHY_CFG_TIMEOUT 100
2574#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2575#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
2576#define AUTO_ALL_MODES 0
2577
2578#ifndef E1000_MASTER_SLAVE
2579
2580#define E1000_MASTER_SLAVE e1000_ms_hw_default
2581#endif
2582
2583#define E1000_TCTL_EXT_BST_MASK 0x000003FF
2584#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00
2585
2586#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
2587
2588#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2589
2590#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2591#define E1000_MC_TBL_SIZE_ICH8LAN 32
2592
2593#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000
2594
2595
2596#define I210_RXPBSIZE_DEFAULT 0x000000A2
2597#define I210_TXPBSIZE_DEFAULT 0x04000014
2598
2599#endif
2600