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8#ifndef __SH_PFC_H
9#define __SH_PFC_H
10
11#include <linux/stringify.h>
12
13enum {
14 PINMUX_TYPE_NONE,
15 PINMUX_TYPE_FUNCTION,
16 PINMUX_TYPE_GPIO,
17 PINMUX_TYPE_OUTPUT,
18 PINMUX_TYPE_INPUT,
19};
20
21#define SH_PFC_PIN_NONE U16_MAX
22
23#define SH_PFC_PIN_CFG_INPUT (1 << 0)
24#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
25#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
26#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
27#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
28 SH_PFC_PIN_CFG_PULL_DOWN)
29#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
30#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
31
32#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
33#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
34
35#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
36 SH_PFC_PIN_VOLTAGE_18_33)
37#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
38 SH_PFC_PIN_VOLTAGE_25_33)
39
40#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
41
42struct sh_pfc_pin {
43 const char *name;
44 unsigned int configs;
45 u16 pin;
46 u16 enum_id;
47};
48
49#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
50 { \
51 .name = #alias, \
52 .pins = n##_pins, \
53 .mux = n##_mux, \
54 .nr_pins = ARRAY_SIZE(n##_pins) + \
55 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
56 }
57#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
58
59struct sh_pfc_pin_group {
60 const char *name;
61 const unsigned int *pins;
62 const unsigned int *mux;
63 unsigned int nr_pins;
64};
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71
72#define VIN_DATA_PIN_GROUP(n, s, ...) \
73 { \
74 .name = #n#s#__VA_ARGS__, \
75 .pins = n##__VA_ARGS__##_pins.data##s, \
76 .mux = n##__VA_ARGS__##_mux.data##s, \
77 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
78 }
79
80union vin_data12 {
81 unsigned int data12[12];
82 unsigned int data10[10];
83 unsigned int data8[8];
84};
85
86union vin_data16 {
87 unsigned int data16[16];
88 unsigned int data12[12];
89 unsigned int data10[10];
90 unsigned int data8[8];
91};
92
93union vin_data {
94 unsigned int data24[24];
95 unsigned int data20[20];
96 unsigned int data16[16];
97 unsigned int data12[12];
98 unsigned int data10[10];
99 unsigned int data8[8];
100 unsigned int data4[4];
101};
102
103#define SH_PFC_FUNCTION(n) \
104 { \
105 .name = #n, \
106 .groups = n##_groups, \
107 .nr_groups = ARRAY_SIZE(n##_groups), \
108 }
109
110struct sh_pfc_function {
111 const char *name;
112 const char * const *groups;
113 unsigned int nr_groups;
114};
115
116struct pinmux_func {
117 u16 enum_id;
118 const char *name;
119};
120
121struct pinmux_cfg_reg {
122 u32 reg;
123 u8 reg_width, field_width;
124#ifdef DEBUG
125 u16 nr_enum_ids;
126#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
127#else
128#define SET_NR_ENUM_IDS(n)
129#endif
130 const u16 *enum_ids;
131 const u8 *var_field_width;
132};
133
134#define GROUP(...) __VA_ARGS__
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146
147#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
148 .reg = r, .reg_width = r_width, \
149 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
150 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
151 (r_width / f_width) * (1 << f_width)), \
152 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
153 { ids }
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166
167#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
168 .reg = r, .reg_width = r_width, \
169 .var_field_width = (const u8 []) { f_widths, 0 }, \
170 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
171 .enum_ids = (const u16 []) { ids }
172
173struct pinmux_drive_reg_field {
174 u16 pin;
175 u8 offset;
176 u8 size;
177};
178
179struct pinmux_drive_reg {
180 u32 reg;
181 const struct pinmux_drive_reg_field fields[8];
182};
183
184#define PINMUX_DRIVE_REG(name, r) \
185 .reg = r, \
186 .fields =
187
188struct pinmux_bias_reg {
189 u32 puen;
190 u32 pud;
191 const u16 pins[32];
192};
193
194#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
195 .puen = r1, \
196 .pud = r2, \
197 .pins =
198
199struct pinmux_ioctrl_reg {
200 u32 reg;
201};
202
203struct pinmux_data_reg {
204 u32 reg;
205 u8 reg_width;
206 const u16 *enum_ids;
207};
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217#define PINMUX_DATA_REG(name, r, r_width, ids) \
218 .reg = r, .reg_width = r_width + \
219 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
220 r_width), \
221 .enum_ids = (const u16 [r_width]) { ids }
222
223struct pinmux_irq {
224 const short *gpios;
225};
226
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230
231#define PINMUX_IRQ(ids...) \
232 { .gpios = (const short []) { ids, -1 } }
233
234struct pinmux_range {
235 u16 begin;
236 u16 end;
237 u16 force;
238};
239
240struct sh_pfc_window {
241 phys_addr_t phys;
242 void __iomem *virt;
243 unsigned long size;
244};
245
246struct sh_pfc_pin_range;
247
248struct sh_pfc {
249 struct device *dev;
250 const struct sh_pfc_soc_info *info;
251
252 void *regs;
253
254 struct sh_pfc_pin_range *ranges;
255 unsigned int nr_ranges;
256
257 unsigned int nr_gpio_pins;
258
259 struct sh_pfc_chip *gpio;
260};
261
262struct sh_pfc_soc_operations {
263 int (*init)(struct sh_pfc *pfc);
264 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
265 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
266 unsigned int bias);
267 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
268};
269
270struct sh_pfc_soc_info {
271 const char *name;
272 const struct sh_pfc_soc_operations *ops;
273
274 struct pinmux_range input;
275 struct pinmux_range output;
276 struct pinmux_range function;
277
278 const struct sh_pfc_pin *pins;
279 unsigned int nr_pins;
280 const struct sh_pfc_pin_group *groups;
281 unsigned int nr_groups;
282 const struct sh_pfc_function *functions;
283 unsigned int nr_functions;
284
285 const struct pinmux_cfg_reg *cfg_regs;
286 const struct pinmux_drive_reg *drive_regs;
287 const struct pinmux_bias_reg *bias_regs;
288 const struct pinmux_ioctrl_reg *ioctrl_regs;
289 const struct pinmux_data_reg *data_regs;
290
291 const u16 *pinmux_data;
292 unsigned int pinmux_data_size;
293
294 const struct pinmux_irq *gpio_irq;
295 unsigned int gpio_irq_size;
296
297 u32 unlock_reg;
298};
299
300u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
301void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
302const struct pinmux_bias_reg *
303sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
304 unsigned int *bit);
305
306extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
307extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
308extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
309extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
310extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
311extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
312extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
313extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
314extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
315extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
316extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
317extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
318extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
319extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
320extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
321extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
322extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
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337#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
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345#define PINMUX_IPSR_NOGP(ipsr, fn) \
346 PINMUX_DATA(fn##_MARK, FN_##fn)
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355#define PINMUX_IPSR_GPSR(ipsr, fn) \
356 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
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365
366#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
367 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
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377#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
378 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
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389#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
390 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
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401#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
402 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
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411#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
412 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
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418
419#define PINMUX_SINGLE(fn) \
420 PINMUX_DATA(fn##_MARK, FN_##fn)
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425
426#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
427 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
428#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
429
430#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
431 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
432 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
433#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
434
435#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
436 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
437 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
438 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
439#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
440
441#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
442 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
443 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
444 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
445#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
446
447#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
448 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
449 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
450 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
451#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
452
453#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
454 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
456#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
457
458#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
459 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
460 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
461#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
462
463#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
464 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
465 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
466#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
467
468#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
469 PORT_GP_CFG_11(bank, fn, sfx, cfg), \
470 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
471#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
472
473#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
474 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
475 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
476 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
477#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
478
479#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
480 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
481 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
482#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
483
484#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
485 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
486 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
487#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
488
489#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
490 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
491 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
492#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
493
494#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
495 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
496 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
497#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
498
499#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
500 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
501 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
502 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
503#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
504
505#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
506 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
507 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
508#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
509
510#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
511 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
512 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
513#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
514
515#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
516 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
517 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
518#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
519
520#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
521 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
522 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
523#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
524
525#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
526 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
527 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
528#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
529
530#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
531 PORT_GP_CFG_25(bank, fn, sfx, cfg), \
532 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
533#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
534
535#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
536 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
537 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
538#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
539
540#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
541 PORT_GP_CFG_27(bank, fn, sfx, cfg), \
542 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
543#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
544
545#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
546 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
547 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
548#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
549
550#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
551 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
552 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
553#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
554
555#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
556 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
557 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
558#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
559
560#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
561 PORT_GP_CFG_31(bank, fn, sfx, cfg), \
562 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
563#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
564
565#define PORT_GP_32_REV(bank, fn, sfx) \
566 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
567 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
568 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
569 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
570 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
571 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
572 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
573 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
574 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
575 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
576 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
577 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
578 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
579 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
580 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
581 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
582
583
584#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
585#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
586
587
588#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
589 { \
590 .pin = (bank * 32) + _pin, \
591 .name = __stringify(_name), \
592 .enum_id = _name##_DATA, \
593 .configs = cfg, \
594 }
595#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
596
597
598#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
599#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
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609
610#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
611 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
612#define GP_ASSIGN_LAST() \
613 GP_LAST = sizeof(union { \
614 char dummy[0] __attribute__((deprecated, \
615 CPU_ALL_GP(_GP_ENTRY, unused), \
616 deprecated)); \
617 })
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621
622
623#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
624
625#define PORT_10(pn, fn, pfx, sfx) \
626 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
627 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
628 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
629 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
630 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
631
632#define PORT_90(pn, fn, pfx, sfx) \
633 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
634 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
635 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
636 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
637 PORT_10(pn+90, fn, pfx##9, sfx)
638
639
640#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
641#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
642
643
644#define PINMUX_GPIO(_pin) \
645 [GPIO_##_pin] = { \
646 .pin = (u16)-1, \
647 .name = __stringify(GPIO_##_pin), \
648 .enum_id = _pin##_DATA, \
649 }
650
651
652#define SH_PFC_PIN_CFG(_pin, cfgs) \
653 { \
654 .pin = _pin, \
655 .name = __stringify(PORT##_pin), \
656 .enum_id = PORT##_pin##_DATA, \
657 .configs = cfgs, \
658 }
659
660
661
662
663#define _PORT_DATA(pn, pfx, sfx) \
664 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
665 PORT##pfx##_OUT, PORT##pfx##_IN)
666#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
667
668
669
670
671
672
673
674
675
676
677#define _PORT_ENTRY(pn, pfx, sfx) \
678 deprecated)); char pfx[pn] __attribute__((deprecated
679#define PORT_ASSIGN_LAST() \
680 PORT_LAST = sizeof(union { \
681 char dummy[0] __attribute__((deprecated, \
682 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
683 deprecated)); \
684 })
685
686
687#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
688 [gpio - (base)] = { \
689 .name = __stringify(gpio), \
690 .enum_id = data_or_mark, \
691 }
692#define GPIO_FN(str) \
693 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
694
695
696
697
698
699#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
700#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
701
702
703#define _NOGP_ALL(pin, name, cfg) PIN_##pin
704#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
705
706
707#define _NOGP_PINMUX(_pin, _name, cfg) \
708 { \
709 .pin = PIN_##_pin, \
710 .name = "PIN_" _name, \
711 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
712 }
713#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
714
715
716
717
718#define PORTCR(nr, reg) \
719 { \
720 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
721 GROUP(2, 2, 1, 3), \
722 GROUP( \
723 \
724 0, 0, 0, 0, \
725 \
726 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
727 \
728 0, 0, \
729 \
730 PORT##nr##_FN0, PORT##nr##_FN1, \
731 PORT##nr##_FN2, PORT##nr##_FN3, \
732 PORT##nr##_FN4, PORT##nr##_FN5, \
733 PORT##nr##_FN6, PORT##nr##_FN7 \
734 )) \
735 }
736
737
738
739
740#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
741
742#include <linux/bug.h>
743#endif
744