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11#ifndef __RK_SPI_H
12#define __RK_SPI_H
13
14struct rockchip_spi {
15 u32 ctrlr0;
16 u32 ctrlr1;
17 u32 enr;
18 u32 ser;
19 u32 baudr;
20 u32 txftlr;
21 u32 rxftlr;
22 u32 txflr;
23 u32 rxflr;
24 u32 sr;
25 u32 ipr;
26 u32 imr;
27 u32 isr;
28 u32 risr;
29 u32 icr;
30 u32 dmacr;
31 u32 dmatdlr;
32 u32 dmardlr;
33 u32 reserved[0xef];
34 u32 txdr[0x100];
35 u32 rxdr[0x100];
36};
37
38
39enum {
40 DFS_SHIFT = 0,
41 DFS_MASK = 3,
42 DFS_4BIT = 0,
43 DFS_8BIT,
44 DFS_16BIT,
45 DFS_RESV,
46
47 CFS_SHIFT = 2,
48 CFS_MASK = 0xf,
49
50 SCPH_SHIFT = 6,
51 SCPH_MASK = 1,
52 SCPH_TOGMID = 0,
53 SCPH_TOGSTA,
54
55 SCOL_SHIFT = 7,
56 SCOL_MASK = 1,
57 SCOL_LOW = 0,
58 SCOL_HIGH,
59
60 CSM_SHIFT = 8,
61 CSM_MASK = 0x3,
62 CSM_KEEP = 0,
63 CSM_HALF,
64 CSM_ONE,
65 CSM_RESV,
66
67 SSN_DELAY_SHIFT = 10,
68 SSN_DELAY_MASK = 1,
69 SSN_DELAY_HALF = 0,
70 SSN_DELAY_ONE = 1,
71
72 SEM_SHIFT = 11,
73 SEM_MASK = 1,
74 SEM_LITTLE = 0,
75 SEM_BIG,
76
77 FBM_SHIFT = 12,
78 FBM_MASK = 1,
79 FBM_MSB = 0,
80 FBM_LSB,
81
82 HALF_WORD_TX_SHIFT = 13,
83 HALF_WORD_MASK = 1,
84 HALF_WORD_ON = 0,
85 HALF_WORD_OFF,
86
87 RXDSD_SHIFT = 14,
88 RXDSD_MASK = 3,
89
90 FRF_SHIFT = 16,
91 FRF_MASK = 3,
92 FRF_SPI = 0,
93 FRF_SSP,
94 FRF_MICROWIRE,
95 FRF_RESV,
96
97 TMOD_SHIFT = 18,
98 TMOD_MASK = 3,
99 TMOD_TR = 0,
100 TMOD_TO,
101 TMOD_RO,
102 TMOD_RESV,
103
104 OMOD_SHIFT = 20,
105 OMOD_MASK = 1,
106 OMOD_MASTER = 0,
107 OMOD_SLAVE,
108};
109
110
111enum {
112 SR_MASK = 0x7f,
113 SR_BUSY = 1 << 0,
114 SR_TF_FULL = 1 << 1,
115 SR_TF_EMPT = 1 << 2,
116 SR_RF_EMPT = 1 << 3,
117 SR_RF_FULL = 1 << 4,
118};
119
120#define ROCKCHIP_SPI_TIMEOUT_MS 1000
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127
128#define ROCKCHIP_SPI_MAX_RATE 50000000
129
130#endif
131