LXR uboot/drivers/spi/spi-sifive.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2018 SiFive, Inc.
   4 * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
   5 *
   6 * SiFive SPI controller driver (master mode only)
   7 */
   8
   9#include <common.h>
  10#include <dm.h>
  11#include <dm/device_compat.h>
  12#include <malloc.h>
  13#include <spi.h>
  14#include <spi-mem.h>
  15#include <wait_bit.h>
  16#include <asm/io.h>
  17#include <linux/bitops.h>
  18#include <linux/log2.h>
  19#include <clk.h>
  20
  21#define SIFIVE_SPI_MAX_CS               32
  22
  23#define SIFIVE_SPI_DEFAULT_DEPTH        8
  24#define SIFIVE_SPI_DEFAULT_BITS         8
  25
  26/* register offsets */
  27#define SIFIVE_SPI_REG_SCKDIV            0x00 /* Serial clock divisor */
  28#define SIFIVE_SPI_REG_SCKMODE           0x04 /* Serial clock mode */
  29#define SIFIVE_SPI_REG_CSID              0x10 /* Chip select ID */
  30#define SIFIVE_SPI_REG_CSDEF             0x14 /* Chip select default */
  31#define SIFIVE_SPI_REG_CSMODE            0x18 /* Chip select mode */
  32#define SIFIVE_SPI_REG_DELAY0            0x28 /* Delay control 0 */
  33#define SIFIVE_SPI_REG_DELAY1            0x2c /* Delay control 1 */
  34#define SIFIVE_SPI_REG_FMT               0x40 /* Frame format */
  35#define SIFIVE_SPI_REG_TXDATA            0x48 /* Tx FIFO data */
  36#define SIFIVE_SPI_REG_RXDATA            0x4c /* Rx FIFO data */
  37#define SIFIVE_SPI_REG_TXMARK            0x50 /* Tx FIFO watermark */
  38#define SIFIVE_SPI_REG_RXMARK            0x54 /* Rx FIFO watermark */
  39#define SIFIVE_SPI_REG_FCTRL             0x60 /* SPI flash interface control */
  40#define SIFIVE_SPI_REG_FFMT              0x64 /* SPI flash instruction format */
  41#define SIFIVE_SPI_REG_IE                0x70 /* Interrupt Enable Register */
  42#define SIFIVE_SPI_REG_IP                0x74 /* Interrupt Pendings Register */
  43
  44/* sckdiv bits */
  45#define SIFIVE_SPI_SCKDIV_DIV_MASK       0xfffU
  46
  47/* sckmode bits */
  48#define SIFIVE_SPI_SCKMODE_PHA           BIT(0)
  49#define SIFIVE_SPI_SCKMODE_POL           BIT(1)
  50#define SIFIVE_SPI_SCKMODE_MODE_MASK     (SIFIVE_SPI_SCKMODE_PHA | \
  51                                          SIFIVE_SPI_SCKMODE_POL)
  52
  53/* csmode bits */
  54#define SIFIVE_SPI_CSMODE_MODE_AUTO      0U
  55#define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
  56#define SIFIVE_SPI_CSMODE_MODE_OFF       3U
  57
  58/* delay0 bits */
  59#define SIFIVE_SPI_DELAY0_CSSCK(x)       ((u32)(x))
  60#define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
  61#define SIFIVE_SPI_DELAY0_SCKCS(x)       ((u32)(x) << 16)
  62#define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
  63
  64/* delay1 bits */
  65#define SIFIVE_SPI_DELAY1_INTERCS(x)     ((u32)(x))
  66#define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
  67#define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((u32)(x) << 16)
  68#define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
  69
  70/* fmt bits */
  71#define SIFIVE_SPI_FMT_PROTO_SINGLE      0U
  72#define SIFIVE_SPI_FMT_PROTO_DUAL        1U
  73#define SIFIVE_SPI_FMT_PROTO_QUAD        2U
  74#define SIFIVE_SPI_FMT_PROTO_MASK        3U
  75#define SIFIVE_SPI_FMT_ENDIAN            BIT(2)
  76#define SIFIVE_SPI_FMT_DIR               BIT(3)
  77#define SIFIVE_SPI_FMT_LEN(x)            ((u32)(x) << 16)
  78#define SIFIVE_SPI_FMT_LEN_MASK          (0xfU << 16)
  79
  80/* txdata bits */
  81#define SIFIVE_SPI_TXDATA_DATA_MASK      0xffU
  82#define SIFIVE_SPI_TXDATA_FULL           BIT(31)
  83
  84/* rxdata bits */
  85#define SIFIVE_SPI_RXDATA_DATA_MASK      0xffU
  86#define SIFIVE_SPI_RXDATA_EMPTY          BIT(31)
  87
  88/* ie and ip bits */
  89#define SIFIVE_SPI_IP_TXWM               BIT(0)
  90#define SIFIVE_SPI_IP_RXWM               BIT(1)
  91
  92/* format protocol */
  93#define SIFIVE_SPI_PROTO_QUAD           4 /* 4 lines I/O protocol transfer */
  94#define SIFIVE_SPI_PROTO_DUAL           2 /* 2 lines I/O protocol transfer */
  95#define SIFIVE_SPI_PROTO_SINGLE         1 /* 1 line I/O protocol transfer */
  96
  97struct sifive_spi {
  98        void            *regs;          /* base address of the registers */
  99        u32             fifo_depth;
 100        u32             bits_per_word;
 101        u32             cs_inactive;    /* Level of the CS pins when inactive*/
 102        u32             freq;
 103        u32             num_cs;
 104        u8              fmt_proto;
 105};
 106
 107static void sifive_spi_prep_device(struct sifive_spi *spi,
 108                                   struct dm_spi_slave_plat *slave_plat)
 109{
 110        /* Update the chip select polarity */
 111        if (slave_plat->mode & SPI_CS_HIGH)
 112                spi->cs_inactive &= ~BIT(slave_plat->cs);
 113        else
 114                spi->cs_inactive |= BIT(slave_plat->cs);
 115        writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
 116
 117        /* Select the correct device */
 118        writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
 119}
 120
 121static int sifive_spi_set_cs(struct sifive_spi *spi,
 122                             struct dm_spi_slave_plat *slave_plat)
 123{
 124        u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
 125
 126        if (slave_plat->mode & SPI_CS_HIGH)
 127                cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
 128
 129        writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
 130
 131        return 0;
 132}
 133
 134static void sifive_spi_clear_cs(struct sifive_spi *spi)
 135{
 136        writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
 137}
 138
 139static void sifive_spi_prep_transfer(struct sifive_spi *spi,
 140                                     struct dm_spi_slave_plat *slave_plat,
 141                                     u8 *rx_ptr)
 142{
 143        u32 cr;
 144
 145        /* Modify the SPI protocol mode */
 146        cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
 147
 148        /* Bits per word ? */
 149        cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
 150        cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
 151
 152        /* LSB first? */
 153        cr &= ~SIFIVE_SPI_FMT_ENDIAN;
 154        if (slave_plat->mode & SPI_LSB_FIRST)
 155                cr |= SIFIVE_SPI_FMT_ENDIAN;
 156
 157        /* Number of wires ? */
 158        cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
 159        switch (spi->fmt_proto) {
 160        case SIFIVE_SPI_PROTO_QUAD:
 161                cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
 162                break;
 163        case SIFIVE_SPI_PROTO_DUAL:
 164                cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
 165                break;
 166        default:
 167                cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
 168                break;
 169        }
 170
 171        /* SPI direction in/out ? */
 172        cr &= ~SIFIVE_SPI_FMT_DIR;
 173        if (!rx_ptr)
 174                cr |= SIFIVE_SPI_FMT_DIR;
 175
 176        writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
 177}
 178
 179static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
 180{
 181        u32 data;
 182
 183        do {
 184                data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
 185        } while (data & SIFIVE_SPI_RXDATA_EMPTY);
 186
 187        if (rx_ptr)
 188                *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
 189}
 190
 191static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
 192{
 193        u32 data;
 194        u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
 195                                SIFIVE_SPI_TXDATA_DATA_MASK;
 196
 197        do {
 198                data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
 199        } while (data & SIFIVE_SPI_TXDATA_FULL);
 200
 201        writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
 202}
 203
 204static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
 205{
 206        return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
 207                                 bit, true, 100, false);
 208}
 209
 210static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
 211                           const void *dout, void *din, unsigned long flags)
 212{
 213        struct udevice *bus = dev->parent;
 214        struct sifive_spi *spi = dev_get_priv(bus);
 215        struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 216        const u8 *tx_ptr = dout;
 217        u8 *rx_ptr = din;
 218        u32 remaining_len;
 219        int ret;
 220
 221        if (flags & SPI_XFER_BEGIN) {
 222                sifive_spi_prep_device(spi, slave_plat);
 223
 224                ret = sifive_spi_set_cs(spi, slave_plat);
 225                if (ret)
 226                        return ret;
 227        }
 228
 229        sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
 230
 231        remaining_len = bitlen / 8;
 232
 233        while (remaining_len) {
 234                unsigned int n_words = min(remaining_len, spi->fifo_depth);
 235                unsigned int tx_words, rx_words;
 236
 237                /* Enqueue n_words for transmission */
 238                for (tx_words = 0; tx_words < n_words; tx_words++) {
 239                        if (!tx_ptr)
 240                                sifive_spi_tx(spi, NULL);
 241                        else
 242                                sifive_spi_tx(spi, tx_ptr++);
 243                }
 244
 245                if (rx_ptr) {
 246                        /* Wait for transmission + reception to complete */
 247                        writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
 248                        ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
 249                        if (ret)
 250                                return ret;
 251
 252                        /* Read out all the data from the RX FIFO */
 253                        for (rx_words = 0; rx_words < n_words; rx_words++)
 254                                sifive_spi_rx(spi, rx_ptr++);
 255                } else {
 256                        /* Wait for transmission to complete */
 257                        ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
 258                        if (ret)
 259                                return ret;
 260                }
 261
 262                remaining_len -= n_words;
 263        }
 264
 265        if (flags & SPI_XFER_END)
 266                sifive_spi_clear_cs(spi);
 267
 268        return 0;
 269}
 270
 271static int sifive_spi_exec_op(struct spi_slave *slave,
 272                              const struct spi_mem_op *op)
 273{
 274        struct udevice *dev = slave->dev;
 275        struct sifive_spi *spi = dev_get_priv(dev->parent);
 276        unsigned long flags = SPI_XFER_BEGIN;
 277        u8 opcode = op->cmd.opcode;
 278        unsigned int pos = 0;
 279        const void *tx_buf = NULL;
 280        void *rx_buf = NULL;
 281        int op_len, i;
 282        int ret;
 283
 284        if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
 285                flags |= SPI_XFER_END;
 286
 287        spi->fmt_proto = op->cmd.buswidth;
 288
 289        /* send the opcode */
 290        ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
 291        if (ret < 0) {
 292                dev_err(dev, "failed to xfer opcode\n");
 293                return ret;
 294        }
 295
 296        op_len = op->addr.nbytes + op->dummy.nbytes;
 297        u8 op_buf[op_len];
 298
 299        /* send the addr + dummy */
 300        if (op->addr.nbytes) {
 301                /* fill address */
 302                for (i = 0; i < op->addr.nbytes; i++)
 303                        op_buf[pos + i] = op->addr.val >>
 304                                (8 * (op->addr.nbytes - i - 1));
 305
 306                pos += op->addr.nbytes;
 307
 308                /* fill dummy */
 309                if (op->dummy.nbytes)
 310                        memset(op_buf + pos, 0xff, op->dummy.nbytes);
 311
 312                /* make sure to set end flag, if no data bytes */
 313                if (!op->data.nbytes)
 314                        flags |= SPI_XFER_END;
 315
 316                spi->fmt_proto = op->addr.buswidth;
 317
 318                ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
 319                if (ret < 0) {
 320                        dev_err(dev, "failed to xfer addr + dummy\n");
 321                        return ret;
 322                }
 323        }
 324
 325        /* send/received the data */
 326        if (op->data.nbytes) {
 327                if (op->data.dir == SPI_MEM_DATA_IN)
 328                        rx_buf = op->data.buf.in;
 329                else
 330                        tx_buf = op->data.buf.out;
 331
 332                spi->fmt_proto = op->data.buswidth;
 333
 334                ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
 335                                      tx_buf, rx_buf, SPI_XFER_END);
 336                if (ret) {
 337                        dev_err(dev, "failed to xfer data\n");
 338                        return ret;
 339                }
 340        }
 341
 342        return 0;
 343}
 344
 345static int sifive_spi_set_speed(struct udevice *bus, uint speed)
 346{
 347        struct sifive_spi *spi = dev_get_priv(bus);
 348        u32 scale;
 349
 350        if (speed > spi->freq)
 351                speed = spi->freq;
 352
 353        /* Cofigure max speed */
 354        scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
 355                                        & SIFIVE_SPI_SCKDIV_DIV_MASK;
 356        writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
 357
 358        return 0;
 359}
 360
 361static int sifive_spi_set_mode(struct udevice *bus, uint mode)
 362{
 363        struct sifive_spi *spi = dev_get_priv(bus);
 364        u32 cr;
 365
 366        /* Switch clock mode bits */
 367        cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
 368                                ~SIFIVE_SPI_SCKMODE_MODE_MASK;
 369        if (mode & SPI_CPHA)
 370                cr |= SIFIVE_SPI_SCKMODE_PHA;
 371        if (mode & SPI_CPOL)
 372                cr |= SIFIVE_SPI_SCKMODE_POL;
 373
 374        writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
 375
 376        return 0;
 377}
 378
 379static int sifive_spi_cs_info(struct udevice *bus, uint cs,
 380                              struct spi_cs_info *info)
 381{
 382        struct sifive_spi *spi = dev_get_priv(bus);
 383
 384        if (cs >= spi->num_cs)
 385                return -EINVAL;
 386
 387        return 0;
 388}
 389
 390static void sifive_spi_init_hw(struct sifive_spi *spi)
 391{
 392        u32 cs_bits;
 393
 394        /* probe the number of CS lines */
 395        spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
 396        writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
 397        cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
 398        writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
 399        if (!cs_bits) {
 400                printf("Could not auto probe CS lines\n");
 401                return;
 402        }
 403
 404        spi->num_cs = ilog2(cs_bits) + 1;
 405        if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
 406                printf("Invalid number of spi slaves\n");
 407                return;
 408        }
 409
 410        /* Watermark interrupts are disabled by default */
 411        writel(0, spi->regs + SIFIVE_SPI_REG_IE);
 412
 413        /* Default watermark FIFO threshold values */
 414        writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
 415        writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
 416
 417        /* Set CS/SCK Delays and Inactive Time to defaults */
 418        writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
 419               spi->regs + SIFIVE_SPI_REG_DELAY0);
 420        writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
 421               spi->regs + SIFIVE_SPI_REG_DELAY1);
 422
 423        /* Exit specialized memory-mapped SPI flash mode */
 424        writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
 425}
 426
 427static int sifive_spi_probe(struct udevice *bus)
 428{
 429        struct sifive_spi *spi = dev_get_priv(bus);
 430        struct clk clkdev;
 431        int ret;
 432
 433        spi->regs = (void *)(ulong)dev_remap_addr(bus);
 434        if (!spi->regs)
 435                return -ENODEV;
 436
 437        spi->fifo_depth = dev_read_u32_default(bus,
 438                                               "sifive,fifo-depth",
 439                                               SIFIVE_SPI_DEFAULT_DEPTH);
 440
 441        spi->bits_per_word = dev_read_u32_default(bus,
 442                                                  "sifive,max-bits-per-word",
 443                                                  SIFIVE_SPI_DEFAULT_BITS);
 444
 445        ret = clk_get_by_index(bus, 0, &clkdev);
 446        if (ret)
 447                return ret;
 448        spi->freq = clk_get_rate(&clkdev);
 449
 450        /* init the sifive spi hw */
 451        sifive_spi_init_hw(spi);
 452
 453        return 0;
 454}
 455
 456static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
 457        .exec_op        = sifive_spi_exec_op,
 458};
 459
 460static const struct dm_spi_ops sifive_spi_ops = {
 461        .xfer           = sifive_spi_xfer,
 462        .set_speed      = sifive_spi_set_speed,
 463        .set_mode       = sifive_spi_set_mode,
 464        .cs_info        = sifive_spi_cs_info,
 465        .mem_ops        = &sifive_spi_mem_ops,
 466};
 467
 468static const struct udevice_id sifive_spi_ids[] = {
 469        { .compatible = "sifive,spi0" },
 470        { }
 471};
 472
 473U_BOOT_DRIVER(sifive_spi) = {
 474        .name   = "sifive_spi",
 475        .id     = UCLASS_SPI,
 476        .of_match = sifive_spi_ids,
 477        .ops    = &sifive_spi_ops,
 478        .priv_auto      = sizeof(struct sifive_spi),
 479        .probe  = sifive_spi_probe,
 480};
 481