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8#include <config.h>
9#include <common.h>
10#include <div64.h>
11#include <fuse.h>
12#include <log.h>
13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/sys_proto.h>
16#include <dm.h>
17#include <errno.h>
18#include <malloc.h>
19#include <linux/delay.h>
20#include <linux/math64.h>
21#include <thermal.h>
22#include <imx_thermal.h>
23
24
25#define TEMPERATURE_HOT_DELTA 5
26#define FACTOR0 10000000
27#define FACTOR1 15423
28#define FACTOR2 4148468
29#define OFFSET 3580661
30#define MEASURE_FREQ 327
31#define TEMPERATURE_MIN -40
32#define TEMPERATURE_HOT 85
33#define TEMPERATURE_MAX 125
34
35#define TEMPSENSE0_TEMP_CNT_SHIFT 8
36#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
37#define TEMPSENSE0_FINISHED (1 << 2)
38#define TEMPSENSE0_MEASURE_TEMP (1 << 1)
39#define TEMPSENSE0_POWER_DOWN (1 << 0)
40#define MISC0_REFTOP_SELBIASOFF (1 << 3)
41#define TEMPSENSE1_MEASURE_FREQ 0xffff
42
43struct thermal_data {
44 unsigned int fuse;
45 int critical;
46 int minc;
47 int maxc;
48};
49
50#if defined(CONFIG_MX6)
51static int read_cpu_temperature(struct udevice *dev)
52{
53 int temperature;
54 unsigned int reg, n_meas;
55 const struct imx_thermal_plat *pdata = dev_get_plat(dev);
56 struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
57 struct thermal_data *priv = dev_get_priv(dev);
58 u32 fuse = priv->fuse;
59 int t1, n1;
60 s64 c1, c2;
61 s64 temp64;
62 s32 rem;
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70 n1 = fuse >> 20;
71 t1 = 25;
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92 temp64 = FACTOR0;
93 temp64 *= 1000000;
94 temp64 = div_s64_rem(temp64, FACTOR1 * n1 - FACTOR2, &rem);
95 c1 = temp64;
96 c2 = n1 * c1 + 1000000 * t1;
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102
103 writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
104 writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
105
106
107 reg = readl(&anatop->tempsense1);
108 reg &= ~TEMPSENSE1_MEASURE_FREQ;
109 reg |= MEASURE_FREQ;
110 writel(reg, &anatop->tempsense1);
111
112
113 writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
114 writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
115 writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
116
117
118 while ((readl(&anatop->tempsense0) &
119 TEMPSENSE0_FINISHED) == 0)
120 udelay(10000);
121
122
123 reg = readl(&anatop->tempsense0);
124 n_meas = (reg & TEMPSENSE0_TEMP_CNT_MASK)
125 >> TEMPSENSE0_TEMP_CNT_SHIFT;
126 writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
127
128
129 temperature = div_s64_rem(c2 - n_meas * c1 + OFFSET, 1000000, &rem);
130
131
132 writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
133 writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
134
135 return temperature;
136}
137#elif defined(CONFIG_MX7)
138static int read_cpu_temperature(struct udevice *dev)
139{
140 unsigned int reg, tmp;
141 unsigned int raw_25c, te1;
142 int temperature;
143 unsigned int *priv = dev_get_priv(dev);
144 u32 fuse = *priv;
145 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
146 ANATOP_BASE_ADDR;
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155 raw_25c = fuse >> 21;
156 if (raw_25c == 0)
157 raw_25c = 25;
158
159 te1 = (fuse >> 9) & 0x1ff;
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166 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr);
167 writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set);
168
169
170 reg = readl(&ccm_anatop->tempsense1);
171 reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK;
172 reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ);
173 writel(reg, &ccm_anatop->tempsense1);
174
175 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr);
176 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
177 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
178
179 if (soc_rev() >= CHIP_REV_1_1) {
180 while ((readl(&ccm_anatop->tempsense1) &
181 TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
182 ;
183 reg = readl(&ccm_anatop->tempsense1);
184 tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
185 >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
186 } else {
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193 udelay(10000);
194 reg = readl(&ccm_anatop->tempsense1);
195 tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
196 >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
197 }
198
199 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
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202 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_set);
203 writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_clr);
204
205
206 temperature = tmp - (te1 - raw_25c);
207
208 return temperature;
209}
210#endif
211
212int imx_thermal_get_temp(struct udevice *dev, int *temp)
213{
214 struct thermal_data *priv = dev_get_priv(dev);
215 int cpu_tmp = 0;
216
217 cpu_tmp = read_cpu_temperature(dev);
218
219 while (cpu_tmp >= priv->critical) {
220 printf("CPU Temperature (%dC) too close to max (%dC)",
221 cpu_tmp, priv->maxc);
222 puts(" waiting...\n");
223 udelay(5000000);
224 cpu_tmp = read_cpu_temperature(dev);
225 }
226
227 *temp = cpu_tmp;
228
229 return 0;
230}
231
232static const struct dm_thermal_ops imx_thermal_ops = {
233 .get_temp = imx_thermal_get_temp,
234};
235
236static int imx_thermal_probe(struct udevice *dev)
237{
238 unsigned int fuse = ~0;
239
240 const struct imx_thermal_plat *pdata = dev_get_plat(dev);
241 struct thermal_data *priv = dev_get_priv(dev);
242
243
244 fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
245
246 if (is_soc_type(MXC_SOC_MX6)) {
247
248 if (fuse == 0 || fuse == ~0) {
249 debug("CPU: Thermal invalid data, fuse: 0x%x\n",
250 fuse);
251 return -EPERM;
252 }
253 } else if (is_soc_type(MXC_SOC_MX7)) {
254
255 if ((fuse & 0x3ffff) == 0)
256 return -EPERM;
257
258 if (((fuse & 0x1c0000) >> 18) == 0x6)
259 return -EPERM;
260 }
261
262
263 get_cpu_temp_grade(&priv->minc, &priv->maxc);
264 priv->critical = priv->maxc - TEMPERATURE_HOT_DELTA;
265 priv->fuse = fuse;
266
267 enable_thermal_clk();
268
269 return 0;
270}
271
272U_BOOT_DRIVER(imx_thermal) = {
273 .name = "imx_thermal",
274 .id = UCLASS_THERMAL,
275 .ops = &imx_thermal_ops,
276 .probe = imx_thermal_probe,
277 .priv_auto = sizeof(struct thermal_data),
278 .flags = DM_FLAG_PRE_RELOC,
279};
280