1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF5373 FireEngine board. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5373EVB_H 14#define _M5373EVB_H 15 16#include <linux/stringify.h> 17 18/* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23#define CONFIG_SYS_UART_PORT (0) 24 25#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ 26 27#define CONFIG_SYS_UNIFY_CACHE 28 29#ifdef CONFIG_MCFFEC 30# define CONFIG_SYS_DISCOVER_PHY 31/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 32# ifndef CONFIG_SYS_DISCOVER_PHY 33# define FECDUPLEX FULL 34# define FECSPEED _100BASET 35# endif /* CONFIG_SYS_DISCOVER_PHY */ 36#endif 37 38/* I2C */ 39 40#ifdef CONFIG_MCFFEC 41# define CONFIG_IPADDR 192.162.1.2 42# define CONFIG_NETMASK 255.255.255.0 43# define CONFIG_SERVERIP 192.162.1.1 44# define CONFIG_GATEWAYIP 192.162.1.1 45#endif /* FEC_ENET */ 46 47#define CONFIG_HOSTNAME "M5373EVB" 48#define CONFIG_EXTRA_ENV_SETTINGS \ 49 "netdev=eth0\0" \ 50 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 51 "u-boot=u-boot.bin\0" \ 52 "load=tftp ${loadaddr) ${u-boot}\0" \ 53 "upd=run load; run prog\0" \ 54 "prog=prot off 0 3ffff;" \ 55 "era 0 3ffff;" \ 56 "cp.b ${loadaddr} 0 ${filesize};" \ 57 "save\0" \ 58 "" 59 60#define CONFIG_PRAM 512 /* 512 KB */ 61 62#define CONFIG_SYS_CLK 80000000 63#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 64 65#define CONFIG_SYS_MBAR 0xFC000000 66 67#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 68 69/* 70 * Low Level Configuration Settings 71 * (address mappings, register initial values, etc.) 72 * You should know what you are doing if you make changes here. 73 */ 74/*----------------------------------------------------------------------- 75 * Definitions for initial stack pointer and data area (in DPRAM) 76 */ 77#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 78#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 79#define CONFIG_SYS_INIT_RAM_CTRL 0x221 80#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 81#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 82 83/*----------------------------------------------------------------------- 84 * Start addresses for the final memory configuration 85 * (Set up by the startup code) 86 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 87 */ 88#define CONFIG_SYS_SDRAM_BASE 0x40000000 89#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 90#define CONFIG_SYS_SDRAM_CFG1 0x53722730 91#define CONFIG_SYS_SDRAM_CFG2 0x56670000 92#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 93#define CONFIG_SYS_SDRAM_EMOD 0x40010000 94#define CONFIG_SYS_SDRAM_MODE 0x018D0000 95 96#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 97 98#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 99 100/* 101 * For booting Linux, the board info and command line data 102 * have to be in the first 8 MB of memory, since this is 103 * the maximum mapped by the Linux kernel during initialization ?? 104 */ 105#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 106#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 107 108/*----------------------------------------------------------------------- 109 * FLASH organization 110 */ 111#ifdef CONFIG_SYS_FLASH_CFI 112# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 113# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 114# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 115#endif 116 117# define CONFIG_SYS_MAX_NAND_DEVICE 1 118# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 119# define CONFIG_SYS_NAND_SIZE 1 120# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 121# define NAND_ALLOW_ERASE_ALL 1 122 123#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 124 125/* Configuration for environment 126 * Environment is embedded in u-boot in the second sector of the flash 127 */ 128 129#define LDS_BOARD_TEXT \ 130 . = DEFINED(env_offset) ? env_offset : .; \ 131 env/embedded.o(.text*); 132 133/*----------------------------------------------------------------------- 134 * Cache Configuration 135 */ 136 137#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 138 CONFIG_SYS_INIT_RAM_SIZE - 8) 139#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 140 CONFIG_SYS_INIT_RAM_SIZE - 4) 141#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 142#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 143 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 144 CF_ACR_EN | CF_ACR_SM_ALL) 145#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 146 CF_CACR_DCM_P) 147 148/*----------------------------------------------------------------------- 149 * Chipselect bank definitions 150 */ 151/* 152 * CS0 - NOR Flash 1, 2, 4, or 8MB 153 * CS1 - CompactFlash and registers 154 * CS2 - NAND Flash 16, 32, or 64MB 155 * CS3 - Available 156 * CS4 - Available 157 * CS5 - Available 158 */ 159#define CONFIG_SYS_CS0_BASE 0 160#define CONFIG_SYS_CS0_MASK 0x007f0001 161#define CONFIG_SYS_CS0_CTRL 0x00001fa0 162 163#define CONFIG_SYS_CS1_BASE 0x10000000 164#define CONFIG_SYS_CS1_MASK 0x001f0001 165#define CONFIG_SYS_CS1_CTRL 0x002A3780 166 167#define CONFIG_SYS_CS2_BASE 0x20000000 168#define CONFIG_SYS_CS2_MASK (16 << 20) 169#define CONFIG_SYS_CS2_CTRL 0x00001f60 170 171#endif /* _M5373EVB_H */ 172