1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * Configuation settings for the AT91SAM9263EK board. 8 */ 9 10#ifndef __CONFIG_H 11#define __CONFIG_H 12 13#include <linux/stringify.h> 14 15/* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19#include <asm/hardware.h> 20 21/* ARM asynchronous clock */ 22#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 23#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 24 25/* 26 * Hardware drivers 27 */ 28 29/* LCD */ 30#define LCD_BPP LCD_COLOR8 31 32/* SDRAM */ 33#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 34#define CONFIG_SYS_SDRAM_SIZE 0x04000000 35 36#define CONFIG_SYS_INIT_SP_ADDR \ 37 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 38 39/* NOR flash, if populated */ 40#ifdef CONFIG_SYS_USE_NORFLASH 41#define PHYS_FLASH_1 0x10000000 42#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 43#define CONFIG_SYS_MAX_FLASH_SECT 256 44 45#define CONFIG_SYS_MONITOR_SEC 1:0-3 46#define CONFIG_SYS_MONITOR_LEN (256 << 10) 47 48/* Address and size of Primary Environment Sector */ 49 50#define CONFIG_EXTRA_ENV_SETTINGS \ 51 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 52 "update=" \ 53 "protect off ${monitor_base} +${filesize};" \ 54 "erase ${monitor_base} +${filesize};" \ 55 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 56 "protect on ${monitor_base} +${filesize}\0" 57 58#ifndef CONFIG_SKIP_LOWLEVEL_INIT 59#define MASTER_PLL_MUL 171 60#define MASTER_PLL_DIV 14 61#define MASTER_PLL_OUT 3 62 63/* clocks */ 64#define CONFIG_SYS_MOR_VAL \ 65 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 66#define CONFIG_SYS_PLLAR_VAL \ 67 (AT91_PMC_PLLAR_29 | \ 68 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 69 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 70 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 71 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 72 73/* PCK/2 = MCK Master Clock from PLLA */ 74#define CONFIG_SYS_MCKR1_VAL \ 75 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 76 AT91_PMC_MCKR_MDIV_2) 77 78/* PCK/2 = MCK Master Clock from PLLA */ 79#define CONFIG_SYS_MCKR2_VAL \ 80 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 81 AT91_PMC_MCKR_MDIV_2) 82 83/* define PDC[31:16] as DATA[31:16] */ 84#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 85/* no pull-up for D[31:16] */ 86#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 87/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 88#define CONFIG_SYS_MATRIX_EBICSA_VAL \ 89 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 90 AT91_MATRIX_CSA_EBI_CS1A) 91 92/* SDRAM */ 93/* SDRAMC_MR Mode register */ 94#define CONFIG_SYS_SDRC_MR_VAL1 0 95/* SDRAMC_TR - Refresh Timer register */ 96#define CONFIG_SYS_SDRC_TR_VAL1 0x13C 97/* SDRAMC_CR - Configuration register*/ 98#define CONFIG_SYS_SDRC_CR_VAL \ 99 (AT91_SDRAMC_NC_9 | \ 100 AT91_SDRAMC_NR_13 | \ 101 AT91_SDRAMC_NB_4 | \ 102 AT91_SDRAMC_CAS_3 | \ 103 AT91_SDRAMC_DBW_32 | \ 104 (1 << 8) | /* Write Recovery Delay */ \ 105 (7 << 12) | /* Row Cycle Delay */ \ 106 (2 << 16) | /* Row Precharge Delay */ \ 107 (2 << 20) | /* Row to Column Delay */ \ 108 (5 << 24) | /* Active to Precharge Delay */ \ 109 (1 << 28)) /* Exit Self Refresh to Active Delay */ 110 111/* Memory Device Register -> SDRAM */ 112#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 113#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 114#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 115#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 116#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 117#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 118#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 119#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 120#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 121#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 122#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 123#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 124#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 125#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 126#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 127#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 128#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 129#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 130 131/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 132#define CONFIG_SYS_SMC0_SETUP0_VAL \ 133 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 134 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 135#define CONFIG_SYS_SMC0_PULSE0_VAL \ 136 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 137 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 138#define CONFIG_SYS_SMC0_CYCLE0_VAL \ 139 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 140#define CONFIG_SYS_SMC0_MODE0_VAL \ 141 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 142 AT91_SMC_MODE_DBW_16 | \ 143 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 144 145/* user reset enable */ 146#define CONFIG_SYS_RSTC_RMR_VAL \ 147 (AT91_RSTC_KEY | \ 148 AT91_RSTC_MR_URSTEN | \ 149 AT91_RSTC_MR_ERSTL(15)) 150 151/* Disable Watchdog */ 152#define CONFIG_SYS_WDTC_WDMR_VAL \ 153 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 154 AT91_WDT_MR_WDV(0xfff) | \ 155 AT91_WDT_MR_WDDIS | \ 156 AT91_WDT_MR_WDD(0xfff)) 157 158#endif 159#include <linux/stringify.h> 160#endif 161 162/* NAND flash */ 163#ifdef CONFIG_CMD_NAND 164#define CONFIG_SYS_MAX_NAND_DEVICE 1 165#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 166#define CONFIG_SYS_NAND_DBW_8 1 167/* our ALE is AD21 */ 168#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 169/* our CLE is AD22 */ 170#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 171#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 172#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 173#endif 174 175/* USB */ 176#define CONFIG_USB_ATMEL 177#define CONFIG_USB_ATMEL_CLK_SEL_PLLB 178#define CONFIG_USB_OHCI_NEW 1 179#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 180#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 181#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 182#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 183 184#endif 185