1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2014 Freescale Semiconductor 5 */ 6 7#ifndef __LS2_COMMON_H 8#define __LS2_COMMON_H 9 10#include <asm/arch/stream_id_lsch3.h> 11#include <asm/arch/config.h> 12 13/* Link Definitions */ 14#ifdef CONFIG_TFABOOT 15#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 16#else 17#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 18#endif 19 20/* We need architecture specific misc initializations */ 21 22/* Link Definitions */ 23 24#ifndef CONFIG_SYS_FSL_DDR4 25#define CONFIG_SYS_DDR_RAW_TIMING 26#endif 27 28#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 29 30#define CONFIG_VERY_BIG_RAM 31#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 32#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 33#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 34#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 35#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 36 37/* 38 * SMP Definitinos 39 */ 40#define CPU_RELEASE_ADDR secondary_boot_addr 41 42#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 43 44/* 45 * This is not an accurate number. It is used in start.S. The frequency 46 * will be udpated later when get_bus_freq(0) is available. 47 */ 48 49/* GPIO */ 50 51/* I2C */ 52 53/* Serial Port */ 54#define CONFIG_SYS_NS16550_SERIAL 55#define CONFIG_SYS_NS16550_REG_SIZE 1 56#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 57 58/* 59 * During booting, IFC is mapped at the region of 0x30000000. 60 * But this region is limited to 256MB. To accommodate NOR, promjet 61 * and FPGA. This region is divided as below: 62 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 63 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 64 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 65 * 66 * To accommodate bigger NOR flash and other devices, we will map IFC 67 * chip selects to as below: 68 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 69 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 70 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 71 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 72 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 73 * 74 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 75 * CONFIG_SYS_FLASH_BASE has the final address (core view) 76 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 77 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 78 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 79 */ 80 81#define CONFIG_SYS_FLASH_BASE 0x580000000ULL 82#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 83#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 84 85#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 86#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 87 88#ifndef __ASSEMBLY__ 89unsigned long long get_qixis_addr(void); 90#endif 91#define QIXIS_BASE get_qixis_addr() 92#define QIXIS_BASE_PHYS 0x20000000 93#define QIXIS_BASE_PHYS_EARLY 0xC000000 94#define QIXIS_STAT_PRES1 0xb 95#define QIXIS_SDID_MASK 0x07 96#define QIXIS_ESDHC_NO_ADAPTER 0x7 97 98#define CONFIG_SYS_NAND_BASE 0x530000000ULL 99#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 100 101/* MC firmware */ 102/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 103#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 104#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 105#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 106#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 107/* For LS2085A */ 108#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 109#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 110 111/* 112 * Carve out a DDR region which will not be used by u-boot/Linux 113 * 114 * It will be used by MC and Debug Server. The MC region must be 115 * 512MB aligned, so the min size to hide is 512MB. 116 */ 117#ifdef CONFIG_FSL_MC_ENET 118#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) 119#endif 120 121/* Miscellaneous configurable options */ 122 123/* Physical Memory Map */ 124/* fixme: these need to be checked against the board */ 125 126#define CONFIG_HWCONFIG 127#define HWCONFIG_BUFFER_SIZE 128 128 129/* Initial environment variables */ 130#define CONFIG_EXTRA_ENV_SETTINGS \ 131 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 132 "loadaddr=0x80100000\0" \ 133 "kernel_addr=0x100000\0" \ 134 "ramdisk_addr=0x800000\0" \ 135 "ramdisk_size=0x2000000\0" \ 136 "fdt_high=0xa0000000\0" \ 137 "initrd_high=0xffffffffffffffff\0" \ 138 "kernel_start=0x581000000\0" \ 139 "kernel_load=0xa0000000\0" \ 140 "kernel_size=0x2800000\0" \ 141 "console=ttyAMA0,38400n8\0" \ 142 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 143 " 0x580e00000 \0" 144 145/* Monitor Command Prompt */ 146#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 147#define CONFIG_SYS_MAXARGS 64 /* max command args */ 148 149#define CONFIG_SPL_BSS_START_ADDR 0x80100000 150#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 151#define CONFIG_SPL_MAX_SIZE 0x16000 152#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 153#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 154 155#ifdef CONFIG_NAND_BOOT 156#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 157#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 158#endif 159#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 160#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 161#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 162 163#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 164 165#include <asm/arch/soc.h> 166 167#endif /* __LS2_COMMON_H */ 168