LXR uboot/include/configs/smartweb.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 *
   7 * (C) Copyright 2010
   8 * Achim Ehrlich <aehrlich@taskit.de>
   9 * taskit GmbH <www.taskit.de>
  10 *
  11 * (C) Copyright 2012
  12 * Markus Hubig <mhubig@imko.de>
  13 * IMKO GmbH <www.imko.de>
  14 *
  15 * (C) Copyright 2014
  16 * Heiko Schocher <hs@denx.de>
  17 * DENX Software Engineering GmbH
  18 *
  19 * Configuation settings for the smartweb.
  20 */
  21
  22#ifndef __CONFIG_H
  23#define __CONFIG_H
  24
  25/*
  26 * SoC must be defined first, before hardware.h is included.
  27 * In this case SoC is defined in boards.cfg.
  28 */
  29#include <asm/hardware.h>
  30#include <linux/sizes.h>
  31
  32/*
  33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
  34 * program. Since the linker has to swallow that define, we must use a pure
  35 * hex number here!
  36 */
  37
  38/* ARM asynchronous clock */
  39#define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  40#define CONFIG_SYS_AT91_MAIN_CLOCK      18432000        /* 18.432MHz crystal */
  41
  42/* misc settings */
  43
  44/* We set the max number of command args high to avoid HUSH bugs. */
  45#define CONFIG_SYS_MAXARGS    32
  46
  47/* setting board specific options */
  48#define CONFIG_SYS_AUTOLOAD "yes"
  49
  50/*
  51 * SDRAM: 1 bank, 64 MB, base address 0x20000000
  52 * Already initialized before u-boot gets started.
  53 */
  54#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS1
  55#define CONFIG_SYS_SDRAM_SIZE           (64 * SZ_1M)
  56
  57/*
  58 * Perform a SDRAM Memtest from the start of SDRAM
  59 * till the beginning of the U-Boot position in RAM.
  60 */
  61
  62/* NAND flash settings */
  63#define CONFIG_SYS_MAX_NAND_DEVICE      1
  64#define CONFIG_SYS_NAND_BASE            ATMEL_BASE_CS3
  65#define CONFIG_SYS_NAND_DBW_8
  66#define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  67#define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  68#define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIN_PC14
  69#define CONFIG_SYS_NAND_READY_PIN       AT91_PIN_PC13
  70
  71/* serial console */
  72#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  73#define CONFIG_USART_ID                 ATMEL_ID_SYS
  74
  75#if !defined(CONFIG_SPL_BUILD)
  76/* USB configuration */
  77#define CONFIG_USB_ATMEL
  78#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  79#define CONFIG_USB_OHCI_NEW
  80#define CONFIG_SYS_USB_OHCI_CPU_INIT
  81#define CONFIG_SYS_USB_OHCI_REGS_BASE   ATMEL_UHP_BASE
  82#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9260"
  83#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
  84
  85/* USB DFU support */
  86
  87#define CONFIG_USB_GADGET_AT91
  88
  89/* DFU class support */
  90#define DFU_MANIFEST_POLL_TIMEOUT       25000
  91#endif
  92
  93/* General Boot Parameter */
  94#define CONFIG_SYS_CBSIZE               512
  95
  96/*
  97 * The NAND Flash partitions:
  98 */
  99#define CONFIG_ENV_RANGE                (SZ_512K)
 100
 101/*
 102 * Predefined environment variables.
 103 * Usefull to define some easy to use boot commands.
 104 */
 105#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 106                                                                        \
 107        "basicargs=console=ttyS0,115200\0"                              \
 108                                                                        \
 109        "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
 110
 111#ifdef CONFIG_SPL_BUILD
 112#define CONFIG_SYS_INIT_SP_ADDR         0x301000
 113#else
 114/*
 115 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
 116 * leaving the correct space for initial global data structure above that
 117 * address while providing maximum stack area below.
 118 */
 119#define CONFIG_SYS_INIT_SP_ADDR \
 120        (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
 121#endif
 122
 123/* Defines for SPL */
 124#define CONFIG_SPL_MAX_SIZE             (SZ_4K)
 125
 126#define CONFIG_SPL_BSS_START_ADDR       CONFIG_SYS_SDRAM_BASE
 127#define CONFIG_SPL_BSS_MAX_SIZE         (SZ_16K)
 128#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
 129                                        CONFIG_SPL_BSS_MAX_SIZE)
 130#define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 131
 132#define CONFIG_SYS_NAND_ENABLE_PIN_SPL  (2*32 + 14)
 133#define CONFIG_SPL_NAND_RAW_ONLY
 134#define CONFIG_SPL_NAND_SOFTECC
 135#define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 136#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 137#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 138
 139#define CONFIG_SYS_NAND_SIZE            (SZ_256M)
 140#define CONFIG_SYS_NAND_ECCSIZE         256
 141#define CONFIG_SYS_NAND_ECCBYTES        3
 142#define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
 143                                          48, 49, 50, 51, 52, 53, 54, 55, \
 144                                          56, 57, 58, 59, 60, 61, 62, 63, }
 145
 146#define CONFIG_SYS_MASTER_CLOCK         (198656000/2)
 147#define AT91_PLL_LOCK_TIMEOUT           1000000
 148#define CONFIG_SYS_AT91_PLLA            0x2060bf09
 149#define CONFIG_SYS_MCKR                 0x100
 150#define CONFIG_SYS_MCKR_CSS             (0x02 | CONFIG_SYS_MCKR)
 151#define CONFIG_SYS_AT91_PLLB            0x10483f0e
 152
 153#define CONFIG_SPL_PAD_TO               CONFIG_SYS_NAND_U_BOOT_OFFS
 154#define CONFIG_SYS_SPL_LEN              CONFIG_SPL_PAD_TO
 155
 156#endif /* __CONFIG_H */
 157