1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 */ 6 7#ifndef __PFE_ETH_H__ 8#define __PFE_ETH_H__ 9 10#include <linux/bitops.h> 11#include <linux/sizes.h> 12#include <asm/io.h> 13#include <miiphy.h> 14#include <malloc.h> 15#include "pfe_driver.h" 16 17#define BMU2_DDR_BASEADDR 0 18#define BMU2_BUF_COUNT (3 * SZ_1K) 19#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT) 20 21#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE) 22#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE) 23#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE) 24#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE) 25 26#define HIF_DESC_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE) 27#define HIF_RX_DESC_SIZE (16 * HIF_RX_DESC_NT) 28#define HIF_TX_DESC_SIZE (16 * HIF_TX_DESC_NT) 29 30#define UTIL_CODE_BASEADDR 0x780000 31#define UTIL_CODE_SIZE (128 * SZ_1K) 32 33#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE) 34#define UTIL_DDR_DATA_SIZE (64 * SZ_1K) 35 36#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE) 37#define CLASS_DDR_DATA_SIZE (32 * SZ_1K) 38 39#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE) 40#define TMU_DDR_DATA_SIZE (32 * SZ_1K) 41 42#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE) 43#define TMU_LLM_QUEUE_LEN (16 * 256) 44 /* Must be power of two and at least 16 * 8 = 128 bytes */ 45#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) 46 /* (4 TMU's x 16 queues x queue_len) */ 47 48#define ROUTE_TABLE_BASEADDR 0x800000 49#define ROUTE_TABLE_HASH_BITS_MAX 15 /* 32K entries */ 50#define ROUTE_TABLE_HASH_BITS 8 /* 256 entries */ 51#define ROUTE_TABLE_SIZE (BIT(ROUTE_TABLE_HASH_BITS_MAX) \ 52 * CLASS_ROUTE_SIZE) 53 54#define PFE_TOTAL_DATA_SIZE (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE) 55 56#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M) 57#error DDR mapping above 12MiB 58#endif 59 60/* LMEM Mapping */ 61#define BMU1_LMEM_BASEADDR 0 62#define BMU1_BUF_COUNT 256 63#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT) 64 65struct gemac_s { 66 void *gemac_base; 67 void *egpi_base; 68 69 /* GEMAC config */ 70 int gemac_mode; 71 int gemac_speed; 72 int gemac_duplex; 73 int flags; 74 /* phy iface */ 75 int phy_address; 76 int phy_mode; 77 struct mii_dev *bus; 78 79}; 80 81struct pfe_mdio_info { 82 void *reg_base; 83 char *name; 84}; 85 86struct pfe_eth_dev { 87 int gemac_port; 88 struct gemac_s *gem; 89 struct pfe_ddr_address pfe_addr; 90 struct udevice *dev; 91#ifdef CONFIG_PHYLIB 92 struct phy_device *phydev; 93#endif 94}; 95 96int pfe_remove(struct pfe_ddr_address *pfe_addr); 97struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info); 98void pfe_set_mdio(int dev_id, struct mii_dev *bus); 99void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode); 100int gemac_initialize(struct bd_info *bis, int dev_id, char *devname); 101int pfe_init(struct pfe_ddr_address *pfe_addr); 102int pfe_eth_board_init(struct udevice *dev); 103 104#endif /* __PFE_ETH_H__ */ 105