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11#ifndef _PCI_H
12#define _PCI_H
13
14#define PCI_CFG_SPACE_SIZE 256
15#define PCI_CFG_SPACE_EXP_SIZE 4096
16
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20
21#define PCI_STD_HEADER_SIZEOF 64
22#define PCI_VENDOR_ID 0x00
23#define PCI_DEVICE_ID 0x02
24#define PCI_COMMAND 0x04
25#define PCI_COMMAND_IO 0x1
26#define PCI_COMMAND_MEMORY 0x2
27#define PCI_COMMAND_MASTER 0x4
28#define PCI_COMMAND_SPECIAL 0x8
29#define PCI_COMMAND_INVALIDATE 0x10
30#define PCI_COMMAND_VGA_PALETTE 0x20
31#define PCI_COMMAND_PARITY 0x40
32#define PCI_COMMAND_WAIT 0x80
33#define PCI_COMMAND_SERR 0x100
34#define PCI_COMMAND_FAST_BACK 0x200
35
36#define PCI_STATUS 0x06
37#define PCI_STATUS_CAP_LIST 0x10
38#define PCI_STATUS_66MHZ 0x20
39#define PCI_STATUS_UDF 0x40
40#define PCI_STATUS_FAST_BACK 0x80
41#define PCI_STATUS_PARITY 0x100
42#define PCI_STATUS_DEVSEL_MASK 0x600
43#define PCI_STATUS_DEVSEL_FAST 0x000
44#define PCI_STATUS_DEVSEL_MEDIUM 0x200
45#define PCI_STATUS_DEVSEL_SLOW 0x400
46#define PCI_STATUS_SIG_TARGET_ABORT 0x800
47#define PCI_STATUS_REC_TARGET_ABORT 0x1000
48#define PCI_STATUS_REC_MASTER_ABORT 0x2000
49#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
50#define PCI_STATUS_DETECTED_PARITY 0x8000
51
52#define PCI_CLASS_REVISION 0x08
53
54#define PCI_REVISION_ID 0x08
55#define PCI_CLASS_PROG 0x09
56#define PCI_CLASS_DEVICE 0x0a
57#define PCI_CLASS_CODE 0x0b
58#define PCI_CLASS_SUB_CODE 0x0a
59
60#define PCI_CACHE_LINE_SIZE 0x0c
61#define PCI_LATENCY_TIMER 0x0d
62#define PCI_HEADER_TYPE 0x0e
63#define PCI_HEADER_TYPE_NORMAL 0
64#define PCI_HEADER_TYPE_BRIDGE 1
65#define PCI_HEADER_TYPE_CARDBUS 2
66
67#define PCI_BIST 0x0f
68#define PCI_BIST_CODE_MASK 0x0f
69#define PCI_BIST_START 0x40
70#define PCI_BIST_CAPABLE 0x80
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77
78#define PCI_BASE_ADDRESS_0 0x10
79#define PCI_BASE_ADDRESS_1 0x14
80#define PCI_BASE_ADDRESS_2 0x18
81#define PCI_BASE_ADDRESS_3 0x1c
82#define PCI_BASE_ADDRESS_4 0x20
83#define PCI_BASE_ADDRESS_5 0x24
84#define PCI_BASE_ADDRESS_SPACE 0x01
85#define PCI_BASE_ADDRESS_SPACE_IO 0x01
86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00
89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02
90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04
91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08
92#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
93#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
94
95
96
97#define pci_offset_to_barnum(offset) \
98 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
99
100
101#define PCI_CARDBUS_CIS 0x28
102#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
103#define PCI_SUBSYSTEM_ID 0x2e
104#define PCI_ROM_ADDRESS 0x30
105#define PCI_ROM_ADDRESS_ENABLE 0x01
106#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
107
108#define PCI_CAPABILITY_LIST 0x34
109
110
111#define PCI_INTERRUPT_LINE 0x3c
112#define PCI_INTERRUPT_PIN 0x3d
113#define PCI_MIN_GNT 0x3e
114#define PCI_MAX_LAT 0x3f
115
116#define PCI_INTERRUPT_LINE_DISABLE 0xff
117
118
119#define PCI_PRIMARY_BUS 0x18
120#define PCI_SECONDARY_BUS 0x19
121#define PCI_SUBORDINATE_BUS 0x1a
122#define PCI_SEC_LATENCY_TIMER 0x1b
123#define PCI_IO_BASE 0x1c
124#define PCI_IO_LIMIT 0x1d
125#define PCI_IO_RANGE_TYPE_MASK 0x0f
126#define PCI_IO_RANGE_TYPE_16 0x00
127#define PCI_IO_RANGE_TYPE_32 0x01
128#define PCI_IO_RANGE_MASK ~0x0f
129#define PCI_SEC_STATUS 0x1e
130#define PCI_MEMORY_BASE 0x20
131#define PCI_MEMORY_LIMIT 0x22
132#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
133#define PCI_MEMORY_RANGE_MASK ~0x0f
134#define PCI_PREF_MEMORY_BASE 0x24
135#define PCI_PREF_MEMORY_LIMIT 0x26
136#define PCI_PREF_RANGE_TYPE_MASK 0x0f
137#define PCI_PREF_RANGE_TYPE_32 0x00
138#define PCI_PREF_RANGE_TYPE_64 0x01
139#define PCI_PREF_RANGE_MASK ~0x0f
140#define PCI_PREF_BASE_UPPER32 0x28
141#define PCI_PREF_LIMIT_UPPER32 0x2c
142#define PCI_IO_BASE_UPPER16 0x30
143#define PCI_IO_LIMIT_UPPER16 0x32
144
145
146#define PCI_ROM_ADDRESS1 0x38
147
148#define PCI_BRIDGE_CONTROL 0x3e
149#define PCI_BRIDGE_CTL_PARITY 0x01
150#define PCI_BRIDGE_CTL_SERR 0x02
151#define PCI_BRIDGE_CTL_NO_ISA 0x04
152#define PCI_BRIDGE_CTL_VGA 0x08
153#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20
154#define PCI_BRIDGE_CTL_BUS_RESET 0x40
155#define PCI_BRIDGE_CTL_FAST_BACK 0x80
156
157
158#define PCI_CB_CAPABILITY_LIST 0x14
159
160#define PCI_CB_SEC_STATUS 0x16
161#define PCI_CB_PRIMARY_BUS 0x18
162#define PCI_CB_CARD_BUS 0x19
163#define PCI_CB_SUBORDINATE_BUS 0x1a
164#define PCI_CB_LATENCY_TIMER 0x1b
165#define PCI_CB_MEMORY_BASE_0 0x1c
166#define PCI_CB_MEMORY_LIMIT_0 0x20
167#define PCI_CB_MEMORY_BASE_1 0x24
168#define PCI_CB_MEMORY_LIMIT_1 0x28
169#define PCI_CB_IO_BASE_0 0x2c
170#define PCI_CB_IO_BASE_0_HI 0x2e
171#define PCI_CB_IO_LIMIT_0 0x30
172#define PCI_CB_IO_LIMIT_0_HI 0x32
173#define PCI_CB_IO_BASE_1 0x34
174#define PCI_CB_IO_BASE_1_HI 0x36
175#define PCI_CB_IO_LIMIT_1 0x38
176#define PCI_CB_IO_LIMIT_1_HI 0x3a
177#define PCI_CB_IO_RANGE_MASK ~0x03
178
179#define PCI_CB_BRIDGE_CONTROL 0x3e
180#define PCI_CB_BRIDGE_CTL_PARITY 0x01
181#define PCI_CB_BRIDGE_CTL_SERR 0x02
182#define PCI_CB_BRIDGE_CTL_ISA 0x04
183#define PCI_CB_BRIDGE_CTL_VGA 0x08
184#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
185#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40
186#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
187#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
188#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
189#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
190#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
191#define PCI_CB_SUBSYSTEM_ID 0x42
192#define PCI_CB_LEGACY_MODE_BASE 0x44
193
194
195
196
197#define PCI_CAP_LIST_ID 0
198#define PCI_CAP_ID_PM 0x01
199#define PCI_CAP_ID_AGP 0x02
200#define PCI_CAP_ID_VPD 0x03
201#define PCI_CAP_ID_SLOTID 0x04
202#define PCI_CAP_ID_MSI 0x05
203#define PCI_CAP_ID_CHSWP 0x06
204#define PCI_CAP_ID_PCIX 0x07
205#define PCI_CAP_ID_HT 0x08
206#define PCI_CAP_ID_VNDR 0x09
207#define PCI_CAP_ID_DBG 0x0A
208#define PCI_CAP_ID_CCRC 0x0B
209#define PCI_CAP_ID_SHPC 0x0C
210#define PCI_CAP_ID_SSVID 0x0D
211#define PCI_CAP_ID_AGP3 0x0E
212#define PCI_CAP_ID_SECDEV 0x0F
213#define PCI_CAP_ID_EXP 0x10
214#define PCI_CAP_ID_MSIX 0x11
215#define PCI_CAP_ID_SATA 0x12
216#define PCI_CAP_ID_AF 0x13
217#define PCI_CAP_ID_EA 0x14
218#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
219#define PCI_CAP_LIST_NEXT 1
220#define PCI_CAP_FLAGS 2
221#define PCI_CAP_SIZEOF 4
222
223
224
225#define PCI_PM_CAP_VER_MASK 0x0007
226#define PCI_PM_CAP_PME_CLOCK 0x0008
227#define PCI_PM_CAP_AUX_POWER 0x0010
228#define PCI_PM_CAP_DSI 0x0020
229#define PCI_PM_CAP_D1 0x0200
230#define PCI_PM_CAP_D2 0x0400
231#define PCI_PM_CAP_PME 0x0800
232#define PCI_PM_CTRL 4
233#define PCI_PM_CTRL_STATE_MASK 0x0003
234#define PCI_PM_CTRL_PME_ENABLE 0x0100
235#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00
236#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000
237#define PCI_PM_CTRL_PME_STATUS 0x8000
238#define PCI_PM_PPB_EXTENSIONS 6
239#define PCI_PM_PPB_B2_B3 0x40
240#define PCI_PM_BPCC_ENABLE 0x80
241#define PCI_PM_DATA_REGISTER 7
242#define PCI_PM_SIZEOF 8
243
244
245
246#define PCI_AGP_VERSION 2
247#define PCI_AGP_RFU 3
248#define PCI_AGP_STATUS 4
249#define PCI_AGP_STATUS_RQ_MASK 0xff000000
250#define PCI_AGP_STATUS_SBA 0x0200
251#define PCI_AGP_STATUS_64BIT 0x0020
252#define PCI_AGP_STATUS_FW 0x0010
253#define PCI_AGP_STATUS_RATE4 0x0004
254#define PCI_AGP_STATUS_RATE2 0x0002
255#define PCI_AGP_STATUS_RATE1 0x0001
256#define PCI_AGP_COMMAND 8
257#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
258#define PCI_AGP_COMMAND_SBA 0x0200
259#define PCI_AGP_COMMAND_AGP 0x0100
260#define PCI_AGP_COMMAND_64BIT 0x0020
261#define PCI_AGP_COMMAND_FW 0x0010
262#define PCI_AGP_COMMAND_RATE4 0x0004
263#define PCI_AGP_COMMAND_RATE2 0x0002
264#define PCI_AGP_COMMAND_RATE1 0x0001
265#define PCI_AGP_SIZEOF 12
266
267
268
269#define PCI_X_CMD_DPERR_E 0x0001
270#define PCI_X_CMD_ERO 0x0002
271#define PCI_X_CMD_MAX_READ 0x0000
272#define PCI_X_CMD_MAX_SPLIT 0x0030
273#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3)
274
275
276
277
278#define PCI_SID_ESR 2
279#define PCI_SID_ESR_NSLOTS 0x1f
280#define PCI_SID_ESR_FIC 0x20
281#define PCI_SID_CHASSIS_NR 3
282
283
284
285#define PCI_MSI_FLAGS 2
286#define PCI_MSI_FLAGS_64BIT 0x80
287#define PCI_MSI_FLAGS_QSIZE 0x70
288#define PCI_MSI_FLAGS_QMASK 0x0e
289#define PCI_MSI_FLAGS_ENABLE 0x01
290#define PCI_MSI_FLAGS_MASKBIT 0x0100
291#define PCI_MSI_RFU 3
292#define PCI_MSI_ADDRESS_LO 4
293#define PCI_MSI_ADDRESS_HI 8
294#define PCI_MSI_DATA_32 8
295#define PCI_MSI_DATA_64 12
296
297#define PCI_MAX_PCI_DEVICES 32
298#define PCI_MAX_PCI_FUNCTIONS 8
299
300#define PCI_FIND_CAP_TTL 0x48
301#define CAP_START_POS 0x40
302
303
304#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
305#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
306#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
307
308#define PCI_EXT_CAP_ID_ERR 0x01
309#define PCI_EXT_CAP_ID_VC 0x02
310#define PCI_EXT_CAP_ID_DSN 0x03
311#define PCI_EXT_CAP_ID_PWR 0x04
312#define PCI_EXT_CAP_ID_RCLD 0x05
313#define PCI_EXT_CAP_ID_RCILC 0x06
314#define PCI_EXT_CAP_ID_RCEC 0x07
315#define PCI_EXT_CAP_ID_MFVC 0x08
316#define PCI_EXT_CAP_ID_VC9 0x09
317#define PCI_EXT_CAP_ID_RCRB 0x0A
318#define PCI_EXT_CAP_ID_VNDR 0x0B
319#define PCI_EXT_CAP_ID_CAC 0x0C
320#define PCI_EXT_CAP_ID_ACS 0x0D
321#define PCI_EXT_CAP_ID_ARI 0x0E
322#define PCI_EXT_CAP_ID_ATS 0x0F
323#define PCI_EXT_CAP_ID_SRIOV 0x10
324#define PCI_EXT_CAP_ID_MRIOV 0x11
325#define PCI_EXT_CAP_ID_MCAST 0x12
326#define PCI_EXT_CAP_ID_PRI 0x13
327#define PCI_EXT_CAP_ID_AMD_XXX 0x14
328#define PCI_EXT_CAP_ID_REBAR 0x15
329#define PCI_EXT_CAP_ID_DPA 0x16
330#define PCI_EXT_CAP_ID_TPH 0x17
331#define PCI_EXT_CAP_ID_LTR 0x18
332#define PCI_EXT_CAP_ID_SECPCI 0x19
333#define PCI_EXT_CAP_ID_PMUX 0x1A
334#define PCI_EXT_CAP_ID_PASID 0x1B
335#define PCI_EXT_CAP_ID_DPC 0x1D
336#define PCI_EXT_CAP_ID_L1SS 0x1E
337#define PCI_EXT_CAP_ID_PTM 0x1F
338#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
339
340
341#define PCI_EA_NUM_ENT 2
342#define PCI_EA_NUM_ENT_MASK 0x3f
343#define PCI_EA_FIRST_ENT 4
344#define PCI_EA_ES 0x00000007
345#define PCI_EA_BEI 0x000000f0
346
347#define PCI_EA_BEI_VF_BAR0 9
348#define PCI_EA_BEI_VF_BAR5 14
349
350
351#define PCI_EA_IS_64 0x00000002
352#define PCI_EA_FIELD_MASK 0xfffffffc
353
354
355#define PCI_EXP_FLAGS 2
356#define PCI_EXP_FLAGS_VERS 0x000f
357#define PCI_EXP_FLAGS_TYPE 0x00f0
358#define PCI_EXP_TYPE_ROOT_PORT 0x4
359#define PCI_EXP_TYPE_DOWNSTREAM 0x6
360#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8
361#define PCI_EXP_DEVCAP 4
362#define PCI_EXP_DEVCAP_FLR 0x10000000
363#define PCI_EXP_DEVCTL 8
364#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
365#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000
366#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020
367#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040
368#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060
369#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080
370#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0
371#define PCI_EXP_DEVCTL_RELAX_EN 0x0010
372#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
373#define PCI_EXP_DEVCTL_READRQ 0x7000
374#define PCI_EXP_DEVCTL_READRQ_128B 0x0000
375#define PCI_EXP_DEVCTL_READRQ_256B 0x1000
376#define PCI_EXP_DEVCTL_READRQ_512B 0x2000
377#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000
378#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000
379#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000
380#define PCI_EXP_DEVCTL_BCR_FLR 0x8000
381#define PCI_EXP_LNKCAP 12
382#define PCI_EXP_LNKCAP_SLS 0x0000000f
383#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001
384#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002
385#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003
386#define PCI_EXP_LNKCAP_MLW 0x000003f0
387#define PCI_EXP_LNKCAP_DLLLARC 0x00100000
388#define PCI_EXP_LNKCTL 16
389#define PCI_EXP_LNKCTL_RL 0x0020
390#define PCI_EXP_LNKSTA 18
391#define PCI_EXP_LNKSTA_CLS 0x000f
392#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001
393#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002
394#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003
395#define PCI_EXP_LNKSTA_NLW 0x03f0
396#define PCI_EXP_LNKSTA_NLW_SHIFT 4
397#define PCI_EXP_LNKSTA_LT 0x0800
398#define PCI_EXP_LNKSTA_DLLLA 0x2000
399#define PCI_EXP_LNKSTA_LBMS 0x4000
400#define PCI_EXP_SLTCAP 20
401#define PCI_EXP_SLTCAP_PSN 0xfff80000
402#define PCI_EXP_RTCTL 28
403#define PCI_EXP_RTCTL_CRSSVE 0x0010
404#define PCI_EXP_RTCAP 30
405#define PCI_EXP_RTCAP_CRSVIS 0x0001
406#define PCI_EXP_DEVCAP2 36
407#define PCI_EXP_DEVCAP2_ARI 0x00000020
408#define PCI_EXP_DEVCTL2 40
409#define PCI_EXP_DEVCTL2_ARI 0x0020
410#define PCI_EXP_LNKCAP2 44
411#define PCI_EXP_LNKCAP2_SLS 0x000000fe
412#define PCI_EXP_LNKCTL2 48
413#define PCI_EXP_LNKCTL2_TLS 0x000f
414#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001
415#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002
416#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003
417
418
419#define PCI_ERR_CAP 24
420#define PCI_ERR_CAP_FEP(x) ((x) & 31)
421#define PCI_ERR_CAP_ECRC_GENC 0x00000020
422#define PCI_ERR_CAP_ECRC_GENE 0x00000040
423#define PCI_ERR_CAP_ECRC_CHKC 0x00000080
424#define PCI_ERR_CAP_ECRC_CHKE 0x00000100
425
426
427#define PCI_SRIOV_CAP 0x04
428#define PCI_SRIOV_CTRL 0x08
429#define PCI_SRIOV_CTRL_VFE 0x01
430#define PCI_SRIOV_CTRL_MSE 0x08
431#define PCI_SRIOV_CTRL_ARI 0x10
432#define PCI_SRIOV_INITIAL_VF 0x0c
433#define PCI_SRIOV_TOTAL_VF 0x0e
434#define PCI_SRIOV_NUM_VF 0x10
435#define PCI_SRIOV_VF_OFFSET 0x14
436#define PCI_SRIOV_VF_STRIDE 0x16
437#define PCI_SRIOV_VF_DID 0x1a
438
439
440
441#include <pci_ids.h>
442
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449
450#define PCI_CONF1_BUS_SHIFT 16
451#define PCI_CONF1_DEV_SHIFT 11
452#define PCI_CONF1_FUNC_SHIFT 8
453
454#define PCI_CONF1_BUS_MASK 0xff
455#define PCI_CONF1_DEV_MASK 0x1f
456#define PCI_CONF1_FUNC_MASK 0x7
457#define PCI_CONF1_REG_MASK 0xfc
458
459#define PCI_CONF1_ENABLE BIT(31)
460#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
461#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
462#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
463#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
464
465#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
466 (PCI_CONF1_ENABLE | \
467 PCI_CONF1_BUS(bus) | \
468 PCI_CONF1_DEV(dev) | \
469 PCI_CONF1_FUNC(func) | \
470 PCI_CONF1_REG(reg))
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479
480#define PCI_CONF1_EXT_REG_SHIFT 16
481#define PCI_CONF1_EXT_REG_MASK 0xf00
482#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
483
484#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
485 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
486 PCI_CONF1_EXT_REG(reg))
487
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491
492
493
494#define PCIE_ECAM_BUS_SHIFT 20
495#define PCIE_ECAM_DEV_SHIFT 15
496#define PCIE_ECAM_FUNC_SHIFT 12
497
498#define PCIE_ECAM_BUS_MASK 0xff
499#define PCIE_ECAM_DEV_MASK 0x1f
500#define PCIE_ECAM_FUNC_MASK 0x7
501#define PCIE_ECAM_REG_MASK 0xfff
502
503#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
504#define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT)
505#define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT)
506#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
507
508#define PCIE_ECAM_OFFSET(bus, dev, func, where) \
509 (PCIE_ECAM_BUS(bus) | \
510 PCIE_ECAM_DEV(dev) | \
511 PCIE_ECAM_FUNC(func) | \
512 PCIE_ECAM_REG(where))
513
514#ifndef __ASSEMBLY__
515
516#include <dm/pci.h>
517
518#ifdef CONFIG_SYS_PCI_64BIT
519typedef u64 pci_addr_t;
520typedef u64 pci_size_t;
521#else
522typedef unsigned long pci_addr_t;
523typedef unsigned long pci_size_t;
524#endif
525
526struct pci_region {
527 pci_addr_t bus_start;
528 phys_addr_t phys_start;
529 pci_size_t size;
530 unsigned long flags;
531
532 pci_addr_t bus_lower;
533};
534
535#define PCI_REGION_MEM 0x00000000
536#define PCI_REGION_IO 0x00000001
537#define PCI_REGION_TYPE 0x00000001
538#define PCI_REGION_PREFETCH 0x00000008
539
540#define PCI_REGION_SYS_MEMORY 0x00000100
541#define PCI_REGION_RO 0x00000200
542
543static inline void pci_set_region(struct pci_region *reg,
544 pci_addr_t bus_start,
545 phys_addr_t phys_start,
546 pci_size_t size,
547 unsigned long flags) {
548 reg->bus_start = bus_start;
549 reg->phys_start = phys_start;
550 reg->size = size;
551 reg->flags = flags;
552}
553
554typedef int pci_dev_t;
555
556#define PCI_BUS(d) (((d) >> 16) & 0xff)
557
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566
567#define PCI_DEV(d) (((d) >> 11) & 0x1f)
568#define PCI_FUNC(d) (((d) >> 8) & 0x7)
569#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
570
571#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
572#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
573#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
574#define PCI_ANY_ID (~0)
575
576
577#define PCI_TO_BDF(val) ((val) << 8)
578
579struct pci_device_id {
580 unsigned int vendor, device;
581 unsigned int subvendor, subdevice;
582 unsigned int class, class_mask;
583 unsigned long driver_data;
584};
585
586struct pci_controller;
587
588struct pci_config_table {
589 unsigned int vendor, device;
590 unsigned int class;
591 unsigned int bus;
592 unsigned int dev;
593 unsigned int func;
594
595 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
596 struct pci_config_table *);
597 unsigned long priv[3];
598};
599
600extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
601 struct pci_config_table *);
602extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
603 struct pci_config_table *);
604
605#define INDIRECT_TYPE_NO_PCIE_LINK 1
606
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616
617
618struct pci_controller {
619 struct udevice *bus;
620 struct udevice *ctlr;
621 bool skip_auto_config_until_reloc;
622
623 int first_busno;
624 int last_busno;
625
626 volatile unsigned int *cfg_addr;
627 volatile unsigned char *cfg_data;
628
629 int indirect_type;
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631
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639
640
641 struct pci_region *regions;
642 int region_count;
643
644 struct pci_config_table *config_table;
645
646 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
647
648
649 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
650};
651
652#if defined(CONFIG_DM_PCI_COMPAT)
653extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
654 pci_addr_t addr, unsigned long flags);
655extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
656 phys_addr_t addr, unsigned long flags);
657
658#define pci_phys_to_bus(dev, addr, flags) \
659 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
660#define pci_bus_to_phys(dev, addr, flags) \
661 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
662
663#define pci_virt_to_bus(dev, addr, flags) \
664 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
665 (virt_to_phys(addr)), (flags))
666#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
667 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
668 (addr), (flags)), \
669 (len), (map_flags))
670
671#define pci_phys_to_mem(dev, addr) \
672 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
673#define pci_mem_to_phys(dev, addr) \
674 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
675#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
676#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
677
678#define pci_virt_to_mem(dev, addr) \
679 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
680#define pci_mem_to_virt(dev, addr, len, map_flags) \
681 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
682#define pci_virt_to_io(dev, addr) \
683 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
684#define pci_io_to_virt(dev, addr, len, map_flags) \
685 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
686
687
688extern int pci_hose_read_config_byte(struct pci_controller *hose,
689 pci_dev_t dev, int where, u8 *val);
690extern int pci_hose_read_config_word(struct pci_controller *hose,
691 pci_dev_t dev, int where, u16 *val);
692extern int pci_hose_read_config_dword(struct pci_controller *hose,
693 pci_dev_t dev, int where, u32 *val);
694extern int pci_hose_write_config_byte(struct pci_controller *hose,
695 pci_dev_t dev, int where, u8 val);
696extern int pci_hose_write_config_word(struct pci_controller *hose,
697 pci_dev_t dev, int where, u16 val);
698extern int pci_hose_write_config_dword(struct pci_controller *hose,
699 pci_dev_t dev, int where, u32 val);
700#endif
701
702void pciauto_region_init(struct pci_region *res);
703void pciauto_region_align(struct pci_region *res, pci_size_t size);
704void pciauto_config_init(struct pci_controller *hose);
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717
718int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
719 pci_addr_t *bar, bool supports_64bit);
720int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
721
722#if defined(CONFIG_DM_PCI_COMPAT)
723extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
724 pci_dev_t dev, int where, u8 *val);
725extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
726 pci_dev_t dev, int where, u16 *val);
727extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
728 pci_dev_t dev, int where, u8 val);
729extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
730 pci_dev_t dev, int where, u16 val);
731
732extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
733extern void pci_register_hose(struct pci_controller* hose);
734extern struct pci_controller* pci_bus_to_hose(int bus);
735extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
736extern struct pci_controller *pci_get_hose_head(void);
737
738extern int pci_hose_scan(struct pci_controller *hose);
739extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
740
741extern void pciauto_setup_device(struct pci_controller *hose,
742 pci_dev_t dev, int bars_num,
743 struct pci_region *mem,
744 struct pci_region *prefetch,
745 struct pci_region *io);
746extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
747 pci_dev_t dev, int sub_bus);
748extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
749 pci_dev_t dev, int sub_bus);
750extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
751
752extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
753extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
754pci_dev_t pci_find_class(unsigned int find_class, int index);
755
756extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
757 int cap);
758extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
759 u8 hdr_type);
760extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
761 int cap);
762
763int pci_find_next_ext_capability(struct pci_controller *hose,
764 pci_dev_t dev, int start, int cap);
765int pci_hose_find_ext_capability(struct pci_controller *hose,
766 pci_dev_t dev, int cap);
767
768#endif
769
770const char * pci_class_str(u8 class);
771int pci_last_busno(void);
772
773#ifdef CONFIG_MPC85xx
774extern void pci_mpc85xx_init (struct pci_controller *hose);
775#endif
776
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791void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
792 u32 addr);
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804u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
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819pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
820 struct pci_device_id *ids, int *indexp);
821
822
823enum pci_size_t {
824 PCI_SIZE_8,
825 PCI_SIZE_16,
826 PCI_SIZE_32,
827};
828
829struct udevice;
830
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846
847struct pci_child_plat {
848 int devfn;
849 unsigned short vendor;
850 unsigned short device;
851 unsigned int class;
852
853
854 bool is_virtfn;
855 struct udevice *pfdev;
856 int virtid;
857};
858
859
860struct dm_pci_ops {
861
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866
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878
879 int (*read_config)(const struct udevice *bus, pci_dev_t bdf,
880 uint offset, ulong *valuep, enum pci_size_t size);
881
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890
891 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
892 ulong value, enum pci_size_t size);
893};
894
895
896#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
897
898
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903
904pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
905
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921int pci_bind_bus_devices(struct udevice *bus);
922
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935
936int pci_auto_config_devices(struct udevice *bus);
937
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944
945int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
946
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953
954int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
955 struct udevice **devp);
956
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967
968int pci_find_first_device(struct udevice **devp);
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979
980int pci_find_next_device(struct udevice **devp);
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988
989int pci_get_ff(enum pci_size_t size);
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1003int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
1004 int *indexp, struct udevice **devp);
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1015int pci_find_device_id(const struct pci_device_id *ids, int index,
1016 struct udevice **devp);
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1032int dm_pci_hose_probe_bus(struct udevice *bus);
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1047int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
1048 unsigned long *valuep, enum pci_size_t size);
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1060int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1061 unsigned long value, enum pci_size_t size);
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1075int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1076 u32 clr, u32 set);
1077
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1080
1081
1082int dm_pci_read_config(const struct udevice *dev, int offset,
1083 unsigned long *valuep, enum pci_size_t size);
1084
1085int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep);
1086int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep);
1087int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep);
1088
1089int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1090 enum pci_size_t size);
1091
1092int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1093int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1094int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1095
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1100int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1101int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1102int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
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1108
1109int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1110int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1111int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1112int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1113int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1114int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
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1134int pci_generic_mmap_write_config(
1135 const struct udevice *bus,
1136 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1137 void **addrp),
1138 pci_dev_t bdf,
1139 uint offset,
1140 ulong value,
1141 enum pci_size_t size);
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1160int pci_generic_mmap_read_config(
1161 const struct udevice *bus,
1162 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1163 void **addrp),
1164 pci_dev_t bdf,
1165 uint offset,
1166 ulong *valuep,
1167 enum pci_size_t size);
1168
1169#if defined(CONFIG_PCI_SRIOV)
1170
1171
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1173
1174
1175
1176
1177int pci_sriov_init(struct udevice *pdev, int vf_en);
1178
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1184
1185int pci_sriov_get_totalvfs(struct udevice *pdev);
1186#endif
1187
1188#ifdef CONFIG_DM_PCI_COMPAT
1189
1190static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1191 u32 value)
1192{
1193 return pci_write_config32(pcidev, offset, value);
1194}
1195
1196
1197static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1198 u16 value)
1199{
1200 return pci_write_config16(pcidev, offset, value);
1201}
1202
1203
1204static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1205 u8 value)
1206{
1207 return pci_write_config8(pcidev, offset, value);
1208}
1209
1210
1211static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1212 u32 *valuep)
1213{
1214 return pci_read_config32(pcidev, offset, valuep);
1215}
1216
1217
1218static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1219 u16 *valuep)
1220{
1221 return pci_read_config16(pcidev, offset, valuep);
1222}
1223
1224
1225static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1226 u8 *valuep)
1227{
1228 return pci_read_config8(pcidev, offset, valuep);
1229}
1230#endif
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241int dm_pciauto_config_device(struct udevice *dev);
1242
1243
1244
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1247
1248
1249
1250
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1255
1256ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1257
1258
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1260
1261
1262
1263
1264
1265
1266
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1270
1271ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1272 enum pci_size_t size);
1273
1274
1275
1276
1277
1278
1279
1280struct udevice *pci_get_controller(struct udevice *dev);
1281
1282
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1287
1288
1289
1290
1291int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1292 struct pci_region **memp, struct pci_region **prefp);
1293int
1294pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index);
1295
1296
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1301
1302
1303
1304void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1305
1306
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1312
1313u32 dm_pci_read_bar32(const struct udevice *dev, int barnum);
1314
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1319
1320
1321
1322
1323
1324
1325phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, size_t len,
1326 unsigned long mask, unsigned long flags);
1327
1328
1329
1330
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1332
1333
1334
1335
1336
1337
1338pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len,
1339 unsigned long mask, unsigned long flags);
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1359void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
1360 unsigned long mask, unsigned long flags);
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1382
1383int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
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1404
1405int dm_pci_find_capability(struct udevice *dev, int cap);
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1430int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
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1453int dm_pci_find_ext_capability(struct udevice *dev, int cap);
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1460
1461int dm_pci_flr(struct udevice *dev);
1462
1463#define dm_pci_virt_to_bus(dev, addr, flags) \
1464 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), 0, PCI_REGION_TYPE, (flags))
1465#define dm_pci_bus_to_virt(dev, addr, len, mask, flags, map_flags) \
1466({ \
1467 size_t _len = (len); \
1468 phys_addr_t phys_addr = dm_pci_bus_to_phys((dev), (addr), _len, \
1469 (mask), (flags)); \
1470 map_physmem(phys_addr, _len, (map_flags)); \
1471})
1472
1473#define dm_pci_phys_to_mem(dev, addr) \
1474 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM)
1475#define dm_pci_mem_to_phys(dev, addr) \
1476 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM)
1477#define dm_pci_phys_to_io(dev, addr) \
1478 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO)
1479#define dm_pci_io_to_phys(dev, addr) \
1480 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO)
1481
1482#define dm_pci_virt_to_mem(dev, addr) \
1483 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1484#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1485 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \
1486 PCI_REGION_MEM, (map_flags))
1487#define dm_pci_virt_to_io(dev, addr) \
1488 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1489#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1490 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \
1491 PCI_REGION_IO, (map_flags))
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1501
1502int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1503 struct udevice **devp);
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1513int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
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1522struct pci_emul_uc_priv {
1523 struct udevice *client;
1524};
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1528
1529struct dm_pci_emul_ops {
1530
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1539 int (*read_config)(const struct udevice *dev, uint offset,
1540 ulong *valuep, enum pci_size_t size);
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1550 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1551 enum pci_size_t size);
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1562 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1563 enum pci_size_t size);
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1574 int (*write_io)(struct udevice *dev, unsigned int addr,
1575 ulong value, enum pci_size_t size);
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1591 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1592 unsigned long *lenp, void **ptrp);
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1607 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1608 unsigned long len);
1609};
1610
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1612#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1613
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1625int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
1626 struct udevice **containerp, struct udevice **emulp);
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1635int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
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1643extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
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1654#define PCI_DEVICE(vend, dev) \
1655 .vendor = (vend), .device = (dev), \
1656 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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1668#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1669 .vendor = (vend), .device = (dev), \
1670 .subvendor = (subvend), .subdevice = (subdev)
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1681#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1682 .class = (dev_class), .class_mask = (dev_class_mask), \
1683 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1684 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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1697#define PCI_VDEVICE(vend, dev) \
1698 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1699 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
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1706struct pci_driver_entry {
1707 struct driver *driver;
1708 const struct pci_device_id *match;
1709};
1710
1711#define U_BOOT_PCI_DEVICE(__name, __match) \
1712 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1713 .driver = llsym(struct driver, __name, driver), \
1714 .match = __match, \
1715 }
1716
1717#endif
1718#endif
1719