uboot/arch/arm/include/asm/arch-omap3/mmc_host_def.h
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   1/*
   2 * (C) Copyright 2008
   3 * Texas Instruments, <www.ti.com>
   4 * Syed Mohammed Khasim <khasim@ti.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation's version 2 of
  12 * the License.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#ifndef MMC_HOST_DEF_H
  26#define MMC_HOST_DEF_H
  27
  28#include <asm/omap_mmc.h>
  29
  30/* T2 Register definitions */
  31#define T2_BASE                 0x48002000
  32
  33typedef struct t2 {
  34        unsigned char res1[0x274];      /* 0x000 */
  35        unsigned int devconf0;          /* 0x274 */
  36        unsigned char res2[0x060];      /* 0x278 */
  37        unsigned int devconf1;          /* 0x2D8 */
  38        unsigned char res3[0x16C];      /* 0x2DC */
  39        unsigned int ctl_prog_io1;      /* 0x448 */
  40        unsigned char res4[0x0D4];      /* 0x44C */
  41        unsigned int pbias_lite;        /* 0x520 */
  42} t2_t;
  43
  44#define MMCSDIO1ADPCLKISEL              (1 << 24)
  45#define MMCSDIO2ADPCLKISEL              (1 << 6)
  46
  47#define EN_MMC1                         (1 << 24)
  48#define EN_MMC2                         (1 << 25)
  49#define EN_MMC3                         (1 << 30)
  50
  51#define PBIASLITEPWRDNZ0                (1 << 1)
  52#define PBIASSPEEDCTRL0                 (1 << 2)
  53#define PBIASLITEPWRDNZ1                (1 << 9)
  54#define PBIASLITEVMODE1                 (1 << 8)
  55#define PBIASLITEVMODE0                 (1 << 0)
  56
  57#define CTLPROGIO1SPEEDCTRL             (1 << 20)
  58
  59/*
  60 * OMAP HSMMC register definitions
  61 */
  62#define OMAP_HSMMC1_BASE        0x4809C000
  63#define OMAP_HSMMC2_BASE        0x480B4000
  64#define OMAP_HSMMC3_BASE        0x480AD000
  65
  66
  67#endif /* MMC_HOST_DEF_H */
  68