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6#ifndef _ASM_ARCH_SDRAM_MSCH_H
7#define _ASM_ARCH_SDRAM_MSCH_H
8
9union noc_ddrtiminga0 {
10 u32 d32;
11 struct {
12 unsigned acttoact : 6;
13 unsigned reserved0 : 2;
14 unsigned rdtomiss : 6;
15 unsigned reserved1 : 2;
16 unsigned wrtomiss : 6;
17 unsigned reserved2 : 2;
18 unsigned readlatency : 8;
19 } b;
20};
21
22union noc_ddrtimingb0 {
23 u32 d32;
24 struct {
25 unsigned rdtowr : 5;
26 unsigned reserved0 : 3;
27 unsigned wrtord : 5;
28 unsigned reserved1 : 3;
29 unsigned rrd : 4;
30 unsigned reserved2 : 4;
31 unsigned faw : 6;
32 unsigned reserved3 : 2;
33 } b;
34};
35
36union noc_ddrtimingc0 {
37 u32 d32;
38 struct {
39 unsigned burstpenalty : 4;
40 unsigned reserved0 : 4;
41 unsigned wrtomwr : 6;
42 unsigned reserved1 : 18;
43 } b;
44};
45
46union noc_devtodev0 {
47 u32 d32;
48 struct {
49 unsigned busrdtord : 3;
50 unsigned reserved0 : 1;
51 unsigned busrdtowr : 3;
52 unsigned reserved1 : 1;
53 unsigned buswrtord : 3;
54 unsigned reserved2 : 1;
55 unsigned buswrtowr : 3;
56 unsigned reserved3 : 17;
57 } b;
58};
59
60union noc_ddrmode {
61 u32 d32;
62 struct {
63 unsigned autoprecharge : 1;
64 unsigned bypassfiltering : 1;
65 unsigned fawbank : 1;
66 unsigned burstsize : 2;
67 unsigned mwrsize : 2;
68 unsigned reserved2 : 1;
69 unsigned forceorder : 8;
70 unsigned forceorderstate : 8;
71 unsigned reserved3 : 8;
72 } b;
73};
74
75union noc_ddr4timing {
76 u32 d32;
77 struct {
78 unsigned ccdl : 3;
79 unsigned wrtordl : 5;
80 unsigned rrdl : 4;
81 unsigned reserved1 : 20;
82 } b;
83};
84
85#endif
86
