1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2012 Vikram Narayananan 4 * <vikram186@gmail.com> 5 * (C) Copyright 2012,2015 Stephen Warren 6 */ 7 8#ifndef _BCM2835_GPIO_H_ 9#define _BCM2835_GPIO_H_ 10 11#define BCM2835_GPIO_COUNT 54 12 13#define BCM2835_GPIO_FSEL_MASK 0x7 14#define BCM2835_GPIO_INPUT 0x0 15#define BCM2835_GPIO_OUTPUT 0x1 16#define BCM2835_GPIO_ALT0 0x4 17#define BCM2835_GPIO_ALT1 0x5 18#define BCM2835_GPIO_ALT2 0x6 19#define BCM2835_GPIO_ALT3 0x7 20#define BCM2835_GPIO_ALT4 0x3 21#define BCM2835_GPIO_ALT5 0x2 22 23#define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1) 24#define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f) 25 26#define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) 27#define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) 28 29struct bcm2835_gpio_regs { 30 u32 gpfsel[6]; 31 u32 reserved1; 32 u32 gpset[2]; 33 u32 reserved2; 34 u32 gpclr[2]; 35 u32 reserved3; 36 u32 gplev[2]; 37 u32 reserved4; 38 u32 gpeds[2]; 39 u32 reserved5; 40 u32 gpren[2]; 41 u32 reserved6; 42 u32 gpfen[2]; 43 u32 reserved7; 44 u32 gphen[2]; 45 u32 reserved8; 46 u32 gplen[2]; 47 u32 reserved9; 48 u32 gparen[2]; 49 u32 reserved10; 50 u32 gppud; 51 u32 gppudclk[2]; 52}; 53 54/** 55 * struct bcm2835_gpio_plat - GPIO platform description 56 * 57 * @base: Base address of GPIO controller 58 */ 59struct bcm2835_gpio_plat { 60 unsigned long base; 61}; 62 63#endif /* _BCM2835_GPIO_H_ */ 64