LXR uboot/arch/arm/mach-kirkwood/include/mach/cpu.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2009
   4 * Marvell Semiconductor <www.marvell.com>
   5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6 */
   7
   8#ifndef _KWCPU_H
   9#define _KWCPU_H
  10
  11#include <asm/system.h>
  12
  13#ifndef __ASSEMBLY__
  14
  15#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
  16                        | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
  17
  18#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)      \
  19                ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
  20
  21#define KW_REG_PCIE_DEVID               (KW_REG_PCIE_BASE + 0x00)
  22#define KW_REG_PCIE_REVID               (KW_REG_PCIE_BASE + 0x08)
  23#define KW_REG_DEVICE_ID                (KW_MPP_BASE + 0x34)
  24#define KW_REG_SYSRST_CNT               (KW_MPP_BASE + 0x50)
  25#define SYSRST_CNT_1SEC_VAL             (25*1000000)
  26#define KW_REG_MPP_OUT_DRV_REG          (KW_MPP_BASE + 0xE0)
  27
  28enum memory_bank {
  29        BANK0,
  30        BANK1,
  31        BANK2,
  32        BANK3
  33};
  34
  35enum kwcpu_winen {
  36        KWCPU_WIN_DISABLE,
  37        KWCPU_WIN_ENABLE
  38};
  39
  40enum kwcpu_target {
  41        KWCPU_TARGET_RESERVED,
  42        KWCPU_TARGET_MEMORY,
  43        KWCPU_TARGET_1RESERVED,
  44        KWCPU_TARGET_SASRAM,
  45        KWCPU_TARGET_PCIE
  46};
  47
  48enum kwcpu_attrib {
  49        KWCPU_ATTR_SASRAM = 0x01,
  50        KWCPU_ATTR_DRAM_CS0 = 0x0e,
  51        KWCPU_ATTR_DRAM_CS1 = 0x0d,
  52        KWCPU_ATTR_DRAM_CS2 = 0x0b,
  53        KWCPU_ATTR_DRAM_CS3 = 0x07,
  54        KWCPU_ATTR_NANDFLASH = 0x2f,
  55        KWCPU_ATTR_SPIFLASH = 0x1e,
  56        KWCPU_ATTR_BOOTROM = 0x1d,
  57        KWCPU_ATTR_PCIE_IO = 0xe0,
  58        KWCPU_ATTR_PCIE_MEM = 0xe8
  59};
  60
  61/*
  62 * Default Device Address MAP BAR values
  63 */
  64#define KW_DEFADR_PCI_MEM       0x90000000
  65#define KW_DEFADR_PCI_IO        0xC0000000
  66#define KW_DEFADR_SASRAM        0xC8010000
  67#define KW_DEFADR_NANDF         0xD8000000
  68#define KW_DEFADR_SPIF          0xE8000000
  69#define KW_DEFADR_BOOTROM       0xF8000000
  70
  71#define KW_DEFADR_PCI_MEM_SIZE  (1024 * 1024 * 256)
  72#define KW_DEFADR_PCI_IO_SIZE   (1024 * 64)
  73
  74struct mbus_win {
  75        u32 base;
  76        u32 size;
  77        u8 target;
  78        u8 attr;
  79};
  80
  81/*
  82 * read feroceon/sheeva core extra feature register
  83 * using co-proc instruction
  84 */
  85static inline unsigned int readfr_extra_feature_reg(void)
  86{
  87        unsigned int val;
  88        asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
  89                        (val)::"cc");
  90        return val;
  91}
  92
  93/*
  94 * write feroceon/sheeva core extra feature register
  95 * using co-proc instruction
  96 */
  97static inline void writefr_extra_feature_reg(unsigned int val)
  98{
  99        asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
 100                        (val):"cc");
 101        isb();
 102}
 103
 104/*
 105 * MBus-L to Mbus Bridge Registers
 106 * Ref: Datasheet sec:A.3
 107 */
 108struct kwwin_registers {
 109        u32 ctrl;
 110        u32 base;
 111        u32 remap_lo;
 112        u32 remap_hi;
 113};
 114
 115/*
 116 * CPU control and status Registers
 117 * Ref: Datasheet sec:A.3.2
 118 */
 119struct kwcpu_registers {
 120        u32 config;     /*0x20100 */
 121        u32 ctrl_stat;  /*0x20104 */
 122        u32 rstoutn_mask; /* 0x20108 */
 123        u32 sys_soft_rst; /* 0x2010C */
 124        u32 ahb_mbus_cause_irq; /* 0x20110 */
 125        u32 ahb_mbus_mask_irq; /* 0x20114 */
 126        u32 pad1[2];
 127        u32 ftdll_config; /* 0x20120 */
 128        u32 pad2;
 129        u32 l2_cfg;     /* 0x20128 */
 130};
 131
 132/*
 133 * GPIO Registers
 134 * Ref: Datasheet sec:A.19
 135 */
 136struct kwgpio_registers {
 137        u32 dout;
 138        u32 oe;
 139        u32 blink_en;
 140        u32 din_pol;
 141        u32 din;
 142        u32 irq_cause;
 143        u32 irq_mask;
 144        u32 irq_level;
 145};
 146
 147/*
 148 * functions
 149 */
 150unsigned int mvebu_sdram_bar(enum memory_bank bank);
 151unsigned int mvebu_sdram_bs(enum memory_bank bank);
 152void mvebu_sdram_size_adjust(enum memory_bank bank);
 153int mvebu_mbus_probe(const struct mbus_win windows[], int count);
 154void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 155                unsigned int gpp0_oe, unsigned int gpp1_oe);
 156int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
 157                unsigned int mpp16_23, unsigned int mpp24_31,
 158                unsigned int mpp32_39, unsigned int mpp40_47,
 159                unsigned int mpp48_55);
 160unsigned int kw_winctrl_calcsize(unsigned int sizeval);
 161#endif /* __ASSEMBLY__ */
 162#endif /* _KWCPU_H */
 163