LXR uboot/arch/arm/mach-mvebu/include/mach/cpu.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2009
   4 * Marvell Semiconductor <www.marvell.com>
   5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6 */
   7
   8#ifndef _MVEBU_CPU_H
   9#define _MVEBU_CPU_H
  10
  11#include <asm/system.h>
  12
  13#ifndef __ASSEMBLY__
  14
  15#define MVEBU_REG_PCIE_DEVID            (MVEBU_REG_PCIE_BASE + 0x00)
  16#define MVEBU_REG_PCIE_REVID            (MVEBU_REG_PCIE_BASE + 0x08)
  17
  18enum memory_bank {
  19        BANK0,
  20        BANK1,
  21        BANK2,
  22        BANK3
  23};
  24
  25enum cpu_winen {
  26        CPU_WIN_DISABLE,
  27        CPU_WIN_ENABLE
  28};
  29
  30enum cpu_target {
  31        CPU_TARGET_DRAM = 0x0,
  32        CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
  33        CPU_TARGET_ETH23 = 0x3,
  34        CPU_TARGET_PCIE02 = 0x4,
  35        CPU_TARGET_ETH01 = 0x7,
  36        CPU_TARGET_PCIE13 = 0x8,
  37        CPU_TARGET_DFX = 0x8,
  38        CPU_TARGET_SASRAM = 0x9,
  39        CPU_TARGET_SATA01 = 0xa, /* A38X */
  40        CPU_TARGET_NAND = 0xd,
  41        CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
  42};
  43
  44enum cpu_attrib {
  45        CPU_ATTR_SASRAM = 0x01,
  46        CPU_ATTR_DRAM_CS0 = 0x0e,
  47        CPU_ATTR_DRAM_CS1 = 0x0d,
  48        CPU_ATTR_DRAM_CS2 = 0x0b,
  49        CPU_ATTR_DRAM_CS3 = 0x07,
  50        CPU_ATTR_NANDFLASH = 0x2f,
  51        CPU_ATTR_SPIFLASH = 0x1e,
  52        CPU_ATTR_SPI0_CS0 = 0x1e,
  53        CPU_ATTR_SPI0_CS1 = 0x5e,
  54        CPU_ATTR_SPI1_CS2 = 0x9a,
  55        CPU_ATTR_BOOTROM = 0x1d,
  56        CPU_ATTR_PCIE_IO = 0xe0,
  57        CPU_ATTR_PCIE_MEM = 0xe8,
  58        CPU_ATTR_DEV_CS0 = 0x3e,
  59        CPU_ATTR_DEV_CS1 = 0x3d,
  60        CPU_ATTR_DEV_CS2 = 0x3b,
  61        CPU_ATTR_DEV_CS3 = 0x37,
  62};
  63
  64#define MVEBU_SDRAM_SIZE_MAX    0xc0000000
  65
  66/*
  67 * Default Device Address MAP BAR values
  68 */
  69#define MBUS_PCI_MAX_PORTS      6
  70#define MBUS_PCI_MEM_BASE       MVEBU_SDRAM_SIZE_MAX
  71#define MBUS_PCI_MEM_SIZE       ((MBUS_PCI_MAX_PORTS * 128) << 20)
  72#define MBUS_PCI_IO_BASE        0xF1100000
  73#define MBUS_PCI_IO_SIZE        ((MBUS_PCI_MAX_PORTS * 64) << 10)
  74#define MBUS_SPI_BASE           0xF4000000
  75#define MBUS_SPI_SIZE           (8 << 20)
  76#define MBUS_DFX_BASE           0xF6000000
  77#define MBUS_DFX_SIZE           (1 << 20)
  78#define MBUS_BOOTROM_BASE       0xF8000000
  79#define MBUS_BOOTROM_SIZE       (8 << 20)
  80
  81struct mbus_win {
  82        u32 base;
  83        u32 size;
  84        u8 target;
  85        u8 attr;
  86};
  87
  88/*
  89 * System registers
  90 * Ref: Datasheet sec:A.28
  91 */
  92struct mvebu_system_registers {
  93#if defined(CONFIG_ARMADA_375)
  94        u8 pad1[0x54];
  95#else
  96        u8 pad1[0x60];
  97#endif
  98        u32 rstoutn_mask; /* 0x60 */
  99        u32 sys_soft_rst; /* 0x64 */
 100};
 101
 102/*
 103 * GPIO Registers
 104 * Ref: Datasheet sec:A.19
 105 */
 106struct kwgpio_registers {
 107        u32 dout;
 108        u32 oe;
 109        u32 blink_en;
 110        u32 din_pol;
 111        u32 din;
 112        u32 irq_cause;
 113        u32 irq_mask;
 114        u32 irq_level;
 115};
 116
 117struct sar_freq_modes {
 118        u8 val;
 119        u8 ffc;         /* Fabric Frequency Configuration */
 120        u32 p_clk;
 121        u32 nb_clk;
 122        u32 d_clk;
 123};
 124
 125/*
 126 * functions
 127 */
 128unsigned int mvebu_sdram_bar(enum memory_bank bank);
 129unsigned int mvebu_sdram_bs(enum memory_bank bank);
 130void mvebu_sdram_size_adjust(enum memory_bank bank);
 131int mvebu_mbus_probe(const struct mbus_win windows[], int count);
 132u32 mvebu_get_nand_clock(void);
 133
 134void __noreturn return_to_bootrom(void);
 135
 136#ifndef CONFIG_DM_MMC
 137int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
 138#endif
 139
 140u32 get_boot_device(void);
 141
 142void get_sar_freq(struct sar_freq_modes *sar_freq);
 143
 144/*
 145 * Highspeed SERDES PHY config init, ported from bin_hdr
 146 * to mainline U-Boot
 147 */
 148int serdes_phy_config(void);
 149
 150/*
 151 * DDR3 init / training code ported from Marvell bin_hdr. Now
 152 * available in mainline U-Boot in:
 153 * drivers/ddr/marvell
 154 */
 155int ddr3_init(void);
 156
 157/* Auto Voltage Scaling */
 158#if defined(CONFIG_ARMADA_38X)
 159void mv_avs_init(void);
 160void mv_rtc_config(void);
 161#else
 162static inline void mv_avs_init(void) {}
 163static inline void mv_rtc_config(void) {}
 164#endif
 165
 166/* A8K dram functions */
 167u64 a8k_dram_scan_ap_sz(void);
 168int a8k_dram_init_banksize(void);
 169
 170/* A3700 dram functions */
 171int a3700_dram_init(void);
 172int a3700_dram_init_banksize(void);
 173
 174/* A3700 PCIe regions fixer for device tree */
 175int a3700_fdt_fix_pcie_regions(void *blob);
 176
 177/*
 178 * get_ref_clk
 179 *
 180 * return: reference clock in MHz (25 or 40)
 181 */
 182u32 get_ref_clk(void);
 183
 184#endif /* __ASSEMBLY__ */
 185#endif /* _MVEBU_CPU_H */
 186